mirror of
https://github.com/torvalds/linux.git
synced 2026-09-24 06:24:02 +02:00
8bf5e84998
Add support for the ISSEI (Intel Silicon Security Engine Interface) HECI PCI devices. Add the necessary PCI handling routines, hardware definitions, register mappings and hardware access routines. This enables the communication via HECI PCI device advertized by BIOS. Reviewed-by: Karol Wachowski <karol.wachowski@linux.intel.com> Co-developed-by: Vitaly Lubart <lubvital@gmail.com> Signed-off-by: Vitaly Lubart <lubvital@gmail.com> Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com> Link: https://patch.msgid.link/20260513-issei-for-upstream-v1-4-f590038678f9@intel.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
30 lines
924 B
Plaintext
30 lines
924 B
Plaintext
# SPDX-License-Identifier: GPL-2.0
|
|
# Copyright (C) 2023-2026 Intel Corporation
|
|
config INTEL_SSEI
|
|
tristate "Intel Silicon Security Engine Interface"
|
|
help
|
|
The ISSEI (Intel Silicon Security Engine Interface)
|
|
subsystem provides a communication channel between the host and the
|
|
Silicon Security Engine.
|
|
Enable this driver to get SPDM and other features on Intel client CPUs
|
|
released in 2024 (Lunar Lake) or later.
|
|
|
|
If selected, the /dev/isseiX device will be created.
|
|
If in doubt, select N.
|
|
|
|
if INTEL_SSEI
|
|
|
|
config INTEL_SSEI_HW_HECI
|
|
tristate "Intel Silicon Security Engine Interface Hardware"
|
|
depends on X86 && PCI
|
|
help
|
|
HECI interface of communication channel between
|
|
the host and the Silicon Security Engine.
|
|
|
|
Implementation of ISSEI communication channel over
|
|
the HECI hardware PCI device.
|
|
This device is available on Intel client CPUs released in 2024
|
|
(Lunar Lake) or later.
|
|
|
|
endif
|