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7cd0c655f0
This driver used to use a lot of page table constants from the architecture code which prevented COMPILE_TEST on other architectures. Now that iommupt provides all of the constants internally there are only two small bumps preventing COMPILE_TEST. - Use the generic functions for the riscv specific phys_to_pfn() and pfn_to_phys() - Use CONFIG_MMIOWB to block off the mmiowb() barrier - Require 64 bit because of writeq use failing compilation on 32 bit Tested-by: Vincent Chen <vincent.chen@sifive.com> Acked-by: Paul Walmsley <pjw@kernel.org> # arch/riscv Reviewed-by: Tomasz Jeznach <tjeznach@rivosinc.com> Tested-by: Tomasz Jeznach <tjeznach@rivosinc.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com> Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
25 lines
731 B
Plaintext
25 lines
731 B
Plaintext
# SPDX-License-Identifier: GPL-2.0-only
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# RISC-V IOMMU support
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config RISCV_IOMMU
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bool "RISC-V IOMMU Support"
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default RISCV
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depends on GENERIC_MSI_IRQ
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depends on (RISCV || COMPILE_TEST) && 64BIT
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select IOMMU_API
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select GENERIC_PT
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select IOMMU_PT
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select IOMMU_PT_RISCV64
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help
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Support for implementations of the RISC-V IOMMU architecture that
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complements the RISC-V MMU capabilities, providing similar address
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translation and protection functions for accesses from I/O devices.
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Say Y here if your SoC includes an IOMMU device implementing
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the RISC-V IOMMU architecture.
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config RISCV_IOMMU_PCI
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def_bool y if RISCV_IOMMU && PCI_MSI
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help
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Support for the PCIe implementation of RISC-V IOMMU architecture.
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