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e71e001271
The RISC-V format is a fairly simple 5 level page table not unlike the x86 one. It has optional support for a single contiguous page size of 64k (16 x 4k). The specification describes a 32-bit format, the general code can support it via a #define but the iommu side implementation has been left off until a user comes. Tested-by: Vincent Chen <vincent.chen@sifive.com> Acked-by: Paul Walmsley <pjw@kernel.org> # arch/riscv Reviewed-by: Tomasz Jeznach <tjeznach@rivosinc.com> Tested-by: Tomasz Jeznach <tjeznach@rivosinc.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com> Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
91 lines
3.0 KiB
Plaintext
91 lines
3.0 KiB
Plaintext
# SPDX-License-Identifier: GPL-2.0-only
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menuconfig GENERIC_PT
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bool "Generic Radix Page Table" if COMPILE_TEST
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help
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Generic library for building radix tree page tables.
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Generic PT provides a set of HW page table formats and a common
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set of APIs to work with them.
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if GENERIC_PT
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config DEBUG_GENERIC_PT
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bool "Extra debugging checks for GENERIC_PT"
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help
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Enable extra run time debugging checks for GENERIC_PT code. This
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incurs a runtime cost and should not be enabled for production
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kernels.
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The kunit tests require this to be enabled to get full coverage.
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config IOMMU_PT
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tristate "IOMMU Page Tables"
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select IOMMU_API
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depends on IOMMU_SUPPORT
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depends on GENERIC_PT
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help
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Generic library for building IOMMU page tables
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IOMMU_PT provides an implementation of the page table operations
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related to struct iommu_domain using GENERIC_PT. It provides a single
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implementation of the page table operations that can be shared by
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multiple drivers.
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if IOMMU_PT
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config IOMMU_PT_AMDV1
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tristate "IOMMU page table for 64-bit AMD IOMMU v1"
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depends on !GENERIC_ATOMIC64 # for cmpxchg64
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help
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iommu_domain implementation for the AMD v1 page table. AMDv1 is the
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"host" page table. It supports granular page sizes of almost every
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power of 2 and decodes the full 64-bit IOVA space.
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Selected automatically by an IOMMU driver that uses this format.
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config IOMMU_PT_VTDSS
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tristate "IOMMU page table for Intel VT-d Second Stage"
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depends on !GENERIC_ATOMIC64 # for cmpxchg64
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help
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iommu_domain implementation for the Intel VT-d's 64 bit 3/4/5
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level Second Stage page table. It is similar to the X86_64 format with
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4K/2M/1G page sizes.
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Selected automatically by an IOMMU driver that uses this format.
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config IOMMU_PT_RISCV64
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tristate "IOMMU page table for RISC-V 64 bit Sv57/Sv48/Sv39"
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depends on !GENERIC_ATOMIC64 # for cmpxchg64
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help
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iommu_domain implementation for RISC-V 64 bit 3/4/5 level page table.
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It supports 4K/2M/1G/512G/256T page sizes and can decode a sign
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extended portion of the 64 bit IOVA space.
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Selected automatically by an IOMMU driver that uses this format.
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config IOMMU_PT_X86_64
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tristate "IOMMU page table for x86 64-bit, 4/5 levels"
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depends on !GENERIC_ATOMIC64 # for cmpxchg64
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help
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iommu_domain implementation for the x86 64-bit 4/5 level page table.
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It supports 4K/2M/1G page sizes and can decode a sign-extended
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portion of the 64-bit IOVA space.
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Selected automatically by an IOMMU driver that uses this format.
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config IOMMU_PT_KUNIT_TEST
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tristate "IOMMU Page Table KUnit Test" if !KUNIT_ALL_TESTS
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depends on KUNIT
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depends on IOMMU_PT_AMDV1 || !IOMMU_PT_AMDV1
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depends on IOMMU_PT_RISCV64 || !IOMMU_PT_RISCV64
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depends on IOMMU_PT_X86_64 || !IOMMU_PT_X86_64
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depends on IOMMU_PT_VTDSS || !IOMMU_PT_VTDSS
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default KUNIT_ALL_TESTS
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help
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Enable kunit tests for GENERIC_PT and IOMMU_PT that covers all the
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enabled page table formats. The test covers most of the GENERIC_PT
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functions provided by the page table format, as well as covering the
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iommu_domain related functions.
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endif
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endif
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