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Build and send the Chain of Trust message to FSP, bundling the DMA-coherent boot parameters that FSP reads at boot time. Signed-off-by: John Hubbard <jhubbard@nvidia.com> Link: https://patch.msgid.link/20260603-b4-blackwell-v13-6-d9f3a06939e0@nvidia.com [acourbot: rename `frts_offset` to `frts_vidmem_offset`.] [acourbot: add note about frts_sysmem_* CoT members.] Co-developed-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
89 lines
2.8 KiB
Rust
89 lines
2.8 KiB
Rust
// SPDX-License-Identifier: GPL-2.0
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// SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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//! MCTP/NVDM protocol types for NVIDIA GPU firmware communication.
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//!
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//! MCTP (Management Component Transport Protocol) carries NVDM (NVIDIA
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//! Data Model) messages between the kernel driver and GPU firmware processors
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//! such as FSP and GSP.
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use kernel::pci::Vendor;
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/// NVDM message type identifiers carried over MCTP.
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#[derive(Debug, Clone, Copy, Default, PartialEq, Eq)]
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#[repr(u8)]
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pub(crate) enum NvdmType {
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#[default]
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/// Chain of Trust boot message.
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Cot = 0x14,
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/// FSP command response.
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FspResponse = 0x15,
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}
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impl TryFrom<u8> for NvdmType {
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type Error = u8;
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fn try_from(value: u8) -> Result<Self, Self::Error> {
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match value {
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x if x == u8::from(Self::Cot) => Ok(Self::Cot),
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x if x == u8::from(Self::FspResponse) => Ok(Self::FspResponse),
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_ => Err(value),
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}
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}
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}
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impl From<NvdmType> for u8 {
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fn from(value: NvdmType) -> Self {
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value as u8
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}
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}
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bitfield! {
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pub(crate) struct MctpHeader(u32), "MCTP transport header for NVIDIA firmware messages." {
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31:31 som as bool, "Start-of-message bit.";
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30:30 eom as bool, "End-of-message bit.";
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29:28 seq as u8, "Packet sequence number.";
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23:16 seid as u8, "Source endpoint ID.";
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}
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}
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impl MctpHeader {
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/// Builds a single-packet MCTP header (`SOM=1`, `EOM=1`, `SEQ=0`, `SEID=0`).
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pub(crate) fn single_packet() -> Self {
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Self::default().set_som(true).set_eom(true)
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}
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/// Returns whether this is a complete single-packet message (`SOM=1` and `EOM=1`).
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pub(crate) fn is_single_packet(self) -> bool {
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self.som() && self.eom()
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}
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}
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/// MCTP message type for PCI vendor-defined messages.
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const MSG_TYPE_VENDOR_PCI: u8 = 0x7e;
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bitfield! {
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pub(crate) struct NvdmHeader(u32), "NVIDIA Vendor-Defined Message header over MCTP." {
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31:24 nvdm_type as u8 ?=> NvdmType, "NVDM message type.";
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23:8 vendor_id as u16, "PCI vendor ID.";
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6:0 msg_type as u8, "MCTP vendor-defined message type.";
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}
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}
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impl NvdmHeader {
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/// Builds an NVDM header for the given message type.
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pub(crate) fn new(nvdm_type: NvdmType) -> Self {
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Self::default()
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.set_msg_type(MSG_TYPE_VENDOR_PCI)
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.set_vendor_id(Vendor::NVIDIA.as_raw())
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.set_nvdm_type(nvdm_type)
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}
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/// Validates this header against the expected NVIDIA NVDM format and type.
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pub(crate) fn validate(self, expected_type: NvdmType) -> bool {
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self.msg_type() == MSG_TYPE_VENDOR_PCI
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&& self.vendor_id() == Vendor::NVIDIA.as_raw()
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&& matches!(self.nvdm_type(), Ok(nvdm_type) if nvdm_type == expected_type)
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}
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}
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