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99676aed1f
Currently Nova code uses `&'a Bar0` a lot. This is `&'a Mmio`, where `Mmio` represents an owned MMIO region; this type only exists as a target for `Deref` so `Bar` and `IoMem` can share code and should be avoided to be named directly. The upcoming I/O projection series would make `Io` trait much simpler to implement, and thus the owned MMIO type would be removed in favour of direct `Io` implementation on `Bar` and `IoMem`. Add lifetime parameter to `Bar0<'a>` and change it to be alias of `&'a pci::Bar<'a, ..>`. This also prepares Nova core so that when I/O projection series land, this could be changed to using a MMIO view type directly which avoids double indirection. Signed-off-by: Gary Guo <gary@garyguo.net> Acked-by: Alexandre Courbot <acourbot@nvidia.com> Reviewed-by: Eliot Courtney <ecourtney@nvidia.com> Link: https://patch.msgid.link/20260602170416.2268531-1-gary@kernel.org [ Rebase onto latest drm-rust-next (Blackwell enablement). - Danilo ] Signed-off-by: Danilo Krummrich <dakr@kernel.org>
33 lines
1017 B
Rust
33 lines
1017 B
Rust
// SPDX-License-Identifier: GPL-2.0
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// SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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use crate::{
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driver::Bar0,
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gpu::{
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Architecture,
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Chipset, //
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},
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};
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mod gb100;
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mod gb202;
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mod gh100;
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pub(super) trait FspHal {
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/// Returns the secure boot status from the architecture-specific `NV_THERM_I2CS_SCRATCH` register.
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fn fsp_boot_status(&self, bar: Bar0<'_>) -> u32;
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/// Returns the FSP Chain of Trust protocol version this chipset advertises.
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fn cot_version(&self) -> u16;
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}
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/// Returns the FSP HAL, or `None` if the architecture doesn't support FSP.
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pub(super) fn fsp_hal(chipset: Chipset) -> Option<&'static dyn FspHal> {
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match chipset.arch() {
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Architecture::Turing | Architecture::Ampere | Architecture::Ada => None,
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Architecture::Hopper => Some(gh100::GH100_HAL),
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Architecture::BlackwellGB10x => Some(gb100::GB100_HAL),
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Architecture::BlackwellGB20x => Some(gb202::GB202_HAL),
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}
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}
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