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d34b42ffb1
Add initial support for correctable error handling which is serviced using system controller event. Currently we only log the errors in dmesg but this serves as a foundation for RAS infrastructure and will be further extended to facilitate other RAS features. Signed-off-by: Raag Jadav <raag.jadav@intel.com> Reviewed-by: Mallesh Koujalagi <mallesh.koujalagi@intel.com> Reviewed-by: Riana Tauro <riana.tauro@intel.com> Link: https://patch.msgid.link/20260428054826.1202076-4-raag.jadav@intel.com Signed-off-by: Riana Tauro <riana.tauro@intel.com>
94 lines
2.6 KiB
C
94 lines
2.6 KiB
C
// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2026 Intel Corporation
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*/
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#include "xe_device.h"
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#include "xe_printk.h"
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#include "xe_ras.h"
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#include "xe_ras_types.h"
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#include "xe_sysctrl.h"
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#include "xe_sysctrl_event_types.h"
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/* Severity of detected errors */
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enum xe_ras_severity {
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XE_RAS_SEV_NOT_SUPPORTED = 0,
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XE_RAS_SEV_CORRECTABLE,
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XE_RAS_SEV_UNCORRECTABLE,
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XE_RAS_SEV_INFORMATIONAL,
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XE_RAS_SEV_MAX
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};
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/* Major IP blocks/components where errors can originate */
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enum xe_ras_component {
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XE_RAS_COMP_NOT_SUPPORTED = 0,
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XE_RAS_COMP_DEVICE_MEMORY,
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XE_RAS_COMP_CORE_COMPUTE,
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XE_RAS_COMP_RESERVED,
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XE_RAS_COMP_PCIE,
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XE_RAS_COMP_FABRIC,
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XE_RAS_COMP_SOC_INTERNAL,
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XE_RAS_COMP_MAX
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};
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static const char *const xe_ras_severities[] = {
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[XE_RAS_SEV_NOT_SUPPORTED] = "Not Supported",
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[XE_RAS_SEV_CORRECTABLE] = "Correctable Error",
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[XE_RAS_SEV_UNCORRECTABLE] = "Uncorrectable Error",
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[XE_RAS_SEV_INFORMATIONAL] = "Informational Error",
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};
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static_assert(ARRAY_SIZE(xe_ras_severities) == XE_RAS_SEV_MAX);
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static const char *const xe_ras_components[] = {
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[XE_RAS_COMP_NOT_SUPPORTED] = "Not Supported",
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[XE_RAS_COMP_DEVICE_MEMORY] = "Device Memory",
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[XE_RAS_COMP_CORE_COMPUTE] = "Core Compute",
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[XE_RAS_COMP_RESERVED] = "Reserved",
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[XE_RAS_COMP_PCIE] = "PCIe",
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[XE_RAS_COMP_FABRIC] = "Fabric",
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[XE_RAS_COMP_SOC_INTERNAL] = "SoC Internal",
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};
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static_assert(ARRAY_SIZE(xe_ras_components) == XE_RAS_COMP_MAX);
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static inline const char *sev_to_str(u8 severity)
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{
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if (severity >= XE_RAS_SEV_MAX)
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severity = XE_RAS_SEV_NOT_SUPPORTED;
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return xe_ras_severities[severity];
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}
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static inline const char *comp_to_str(u8 component)
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{
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if (component >= XE_RAS_COMP_MAX)
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component = XE_RAS_COMP_NOT_SUPPORTED;
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return xe_ras_components[component];
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}
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void xe_ras_counter_threshold_crossed(struct xe_device *xe,
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struct xe_sysctrl_event_response *response)
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{
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struct xe_ras_threshold_crossed *pending = (void *)&response->data;
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struct xe_ras_error_class *errors = pending->counters;
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u32 id, ncounters = pending->ncounters;
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BUILD_BUG_ON(sizeof(response->data) < sizeof(*pending));
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xe_device_assert_mem_access(xe);
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if (!ncounters || ncounters > XE_RAS_NUM_COUNTERS)
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xe_err(xe, "sysctrl: unexpected counter threshold crossed %u\n", ncounters);
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else
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xe_warn(xe, "[RAS]: counter threshold crossed, %u new errors\n", ncounters);
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for (id = 0; id < ncounters && id < XE_RAS_NUM_COUNTERS; id++) {
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u8 severity, component;
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severity = errors[id].common.severity;
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component = errors[id].common.component;
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xe_warn(xe, "[RAS]: %s %s detected\n",
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comp_to_str(component), sev_to_str(severity));
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}
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}
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