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07e769ba3d
Currently, v3d_power_suspend() removes the GPU clock without first
quiescing the GPU's memory interface (AXI). If the clock is cut while the
core still has outstanding AXI transactions in flight, the hardware is
frozen mid-transaction. That corrupted state survives the power cycle, and
the first job submitted after the next resume will cause a GPU hang
accompanied by an L2T "pte invalid" MMU fault.
The hardware already provides a safe-powerdown sequence for this: request
the GMP to stop and wait for outstanding reads/writes to drain
(v3d_idle_axi()), plus the GCA safe shutdown on pre-4.1 HW
(v3d_idle_gca()). The driver implements both, but the runtime PM support
added later never invoked them when powering the GPU down.
Perform the safe-powerdown sequence in v3d_power_suspend() before
disabling the clock, while the core is still powered.
Link: https://github.com/raspberrypi/linux/issues/7443
Link: https://github.com/raspberrypi/linux/issues/7488
Fixes: 458f2a712a ("drm/v3d: Introduce Runtime Power Management")
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Link: https://patch.msgid.link/20260718-v3d-pm-axi-transactions-v1-2-4ecd7729ed70@igalia.com
Signed-off-by: Maíra Canal <mcanal@igalia.com>
97 lines
1.8 KiB
C
97 lines
1.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/* Copyright (C) 2026 Raspberry Pi */
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#include <linux/clk.h>
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#include <drm/drm_print.h>
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#include "v3d_drv.h"
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#include "v3d_regs.h"
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static int
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v3d_resume_sms(struct v3d_dev *v3d)
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{
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if (v3d->ver < V3D_GEN_71)
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return 0;
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V3D_SMS_WRITE(V3D_SMS_TEE_CS, V3D_SMS_CLEAR_POWER_OFF);
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if (wait_for((V3D_GET_FIELD(V3D_SMS_READ(V3D_SMS_TEE_CS),
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V3D_SMS_STATE) == V3D_SMS_IDLE), 100)) {
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drm_err(&v3d->drm, "Failed to power up SMS\n");
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return -ETIMEDOUT;
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}
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v3d_reset_sms(v3d);
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return 0;
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}
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static int
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v3d_suspend_sms(struct v3d_dev *v3d)
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{
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if (v3d->ver < V3D_GEN_71)
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return 0;
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V3D_SMS_WRITE(V3D_SMS_TEE_CS, V3D_SMS_POWER_OFF);
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if (wait_for((V3D_GET_FIELD(V3D_SMS_READ(V3D_SMS_TEE_CS),
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V3D_SMS_STATE) == V3D_SMS_POWER_OFF_STATE), 100)) {
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drm_err(&v3d->drm, "Failed to power off SMS\n");
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return -ETIMEDOUT;
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}
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return 0;
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}
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int v3d_power_suspend(struct device *dev)
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{
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struct drm_device *drm = dev_get_drvdata(dev);
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struct v3d_dev *v3d = to_v3d_dev(drm);
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int ret;
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v3d_irq_disable(v3d);
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v3d_clean_caches(v3d);
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/* Wait until V3D has no active or pending AXI transactions. */
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v3d_idle_axi(v3d, 0);
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v3d_idle_gca(v3d);
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ret = v3d_suspend_sms(v3d);
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if (ret) {
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/* Staying active: undo the GMP STOP_REQ from v3d_idle_axi(). */
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V3D_WRITE(V3D_GMP_CFG(v3d->ver),
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V3D_READ(V3D_GMP_CFG(v3d->ver)) & ~V3D_GMP_CFG_STOP_REQ);
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v3d_irq_enable(v3d);
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return ret;
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}
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clk_disable_unprepare(v3d->clk);
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return 0;
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}
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int v3d_power_resume(struct device *dev)
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{
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struct drm_device *drm = dev_get_drvdata(dev);
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struct v3d_dev *v3d = to_v3d_dev(drm);
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int ret;
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ret = clk_prepare_enable(v3d->clk);
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if (ret)
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return ret;
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ret = v3d_resume_sms(v3d);
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if (ret) {
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clk_disable_unprepare(v3d->clk);
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return ret;
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}
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v3d_init_hw_state(v3d);
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v3d_mmu_set_page_table(v3d);
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v3d_irq_enable(v3d);
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return 0;
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}
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