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4226479f91
struct i915_address_space is used in an opaque fashion in the display parent interface, but it's just one include away from being non-opaque. And anyway the name is rather specific. Switch to using the struct intel_dpt instead, which embeds struct i915_address_space anyway. With the definition hidden in i915_dpt.c, this can't be accidentally made non-opaque, and the type seems rather more generic anyway. We do have to add a new helper i915_dpt_to_vm(), as there's one case in intel_fb_pin_to_dpt() that requires direct access to struct i915_address_space. But this just underlines the point about opacity. Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> Link: https://patch.msgid.link/daa39178c0b0305b010564952d691f06e3cd63ca.1772030909.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
95 lines
2.6 KiB
C
95 lines
2.6 KiB
C
// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2023 Intel Corporation
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*/
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#include "intel_de.h"
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#include "intel_display_regs.h"
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#include "intel_display_types.h"
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#include "intel_dpt.h"
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#include "intel_parent.h"
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#include "skl_universal_plane_regs.h"
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void intel_dpt_configure(struct intel_crtc *crtc)
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{
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struct intel_display *display = to_intel_display(crtc);
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if (DISPLAY_VER(display) == 14) {
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enum pipe pipe = crtc->pipe;
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enum plane_id plane_id;
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for_each_plane_id_on_crtc(crtc, plane_id) {
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if (plane_id == PLANE_CURSOR)
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continue;
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intel_de_rmw(display, PLANE_CHICKEN(pipe, plane_id),
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PLANE_CHICKEN_DISABLE_DPT,
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display->params.enable_dpt ? 0 :
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PLANE_CHICKEN_DISABLE_DPT);
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}
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} else if (DISPLAY_VER(display) == 13) {
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intel_de_rmw(display, CHICKEN_MISC_2,
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CHICKEN_MISC_DISABLE_DPT,
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display->params.enable_dpt ? 0 :
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CHICKEN_MISC_DISABLE_DPT);
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}
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}
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/**
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* intel_dpt_suspend - suspend the memory mapping for all DPT FBs during system suspend
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* @display: display device instance
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*
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* Suspend the memory mapping during system suspend for all framebuffers which
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* are mapped to HW via a GGTT->DPT page table.
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*
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* This function must be called before the mappings in GGTT are suspended calling
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* i915_ggtt_suspend().
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*/
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void intel_dpt_suspend(struct intel_display *display)
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{
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struct drm_framebuffer *drm_fb;
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if (!HAS_DISPLAY(display))
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return;
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mutex_lock(&display->drm->mode_config.fb_lock);
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drm_for_each_fb(drm_fb, display->drm) {
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struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);
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if (fb->dpt)
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intel_parent_dpt_suspend(display, fb->dpt);
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}
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mutex_unlock(&display->drm->mode_config.fb_lock);
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}
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/**
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* intel_dpt_resume - restore the memory mapping for all DPT FBs during system resume
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* @display: display device instance
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*
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* Restore the memory mapping during system resume for all framebuffers which
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* are mapped to HW via a GGTT->DPT page table. The content of these page
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* tables are not stored in the hibernation image during S4 and S3RST->S4
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* transitions, so here we reprogram the PTE entries in those tables.
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*
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* This function must be called after the mappings in GGTT have been restored calling
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* i915_ggtt_resume().
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*/
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void intel_dpt_resume(struct intel_display *display)
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{
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struct drm_framebuffer *drm_fb;
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if (!HAS_DISPLAY(display))
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return;
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mutex_lock(&display->drm->mode_config.fb_lock);
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drm_for_each_fb(drm_fb, display->drm) {
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struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);
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if (fb->dpt)
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intel_parent_dpt_resume(display, fb->dpt);
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}
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mutex_unlock(&display->drm->mode_config.fb_lock);
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}
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