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The hard coded clock rate stored in the PLL state will be removed by
a follow-up change. The clock is calculated instead of
using clock from the PLL divider values. Since this calculated clock
may vary due to fixed point rounding issues, a +-1 kHz variation is
allowed with the request clock rate against the calculated clock rate.
v2:
- Use the stricter +-1 kHz allowed difference.
- Derive the clock from PLL dividers in intel_cx0pll_enable().
- Move corresponding fuzzy check for LT PHY PLLs to this patch.
v3: Reword commit message (Suraj)
Move clock check to intel_dpll and rename it (Suraj)
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://patch.msgid.link/20260119093757.2850233-9-mika.kahola@intel.com
54 lines
2.0 KiB
C
54 lines
2.0 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2020 Intel Corporation
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*/
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#ifndef _INTEL_DPLL_H_
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#define _INTEL_DPLL_H_
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#include <linux/types.h>
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enum pipe;
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struct dpll;
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struct intel_atomic_state;
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struct intel_crtc;
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struct intel_crtc_state;
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struct intel_display;
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struct intel_dpll_hw_state;
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void intel_dpll_init_clock_hook(struct intel_display *display);
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int intel_dpll_crtc_compute_clock(struct intel_atomic_state *state,
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struct intel_crtc *crtc);
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int intel_dpll_crtc_get_dpll(struct intel_atomic_state *state,
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struct intel_crtc *crtc);
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int i9xx_calc_dpll_params(int refclk, struct dpll *clock);
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u32 i9xx_dpll_compute_fp(const struct dpll *dpll);
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void i9xx_dpll_get_hw_state(struct intel_crtc *crtc,
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struct intel_dpll_hw_state *dpll_hw_state);
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void vlv_compute_dpll(struct intel_crtc_state *crtc_state);
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void chv_compute_dpll(struct intel_crtc_state *crtc_state);
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int vlv_force_pll_on(struct intel_display *display, enum pipe pipe,
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const struct dpll *dpll);
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void vlv_force_pll_off(struct intel_display *display, enum pipe pipe);
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void chv_enable_pll(const struct intel_crtc_state *crtc_state);
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void chv_disable_pll(struct intel_display *display, enum pipe pipe);
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void vlv_enable_pll(const struct intel_crtc_state *crtc_state);
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void vlv_disable_pll(struct intel_display *display, enum pipe pipe);
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void i9xx_enable_pll(const struct intel_crtc_state *crtc_state);
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void i9xx_disable_pll(const struct intel_crtc_state *crtc_state);
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bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state,
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struct dpll *best_clock);
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int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
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void i9xx_crtc_clock_get(struct intel_crtc_state *crtc_state);
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void vlv_crtc_clock_get(struct intel_crtc_state *crtc_state);
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void chv_crtc_clock_get(struct intel_crtc_state *crtc_state);
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void assert_pll_enabled(struct intel_display *display, enum pipe pipe);
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void assert_pll_disabled(struct intel_display *display, enum pipe pipe);
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bool intel_dpll_clock_matches(int clock1, int clock2);
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#endif
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