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340db7c4d9
Convert the low-hanging fruits of workaround checks to the workaround framework. Instead of having display structure checks for the workarounds all over, concentrate the checks in intel_display_wa.c. Acked-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patch.msgid.link/20260305100100.332956-17-luciano.coelho@intel.com Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
161 lines
5.3 KiB
C
161 lines
5.3 KiB
C
// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2023 Intel Corporation
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*/
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#include <drm/drm_print.h>
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#include "intel_de.h"
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#include "intel_display_core.h"
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#include "intel_display_regs.h"
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#include "intel_display_wa.h"
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#include "intel_step.h"
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static void gen11_display_wa_apply(struct intel_display *display)
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{
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/* Wa_14010594013 */
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intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, 0, ICL_DELAY_PMRSP);
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}
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static void xe_d_display_wa_apply(struct intel_display *display)
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{
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/* Wa_14013723622 */
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intel_de_rmw(display, CLKREQ_POLICY, CLKREQ_POLICY_MEM_UP_OVRD, 0);
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}
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static void adlp_display_wa_apply(struct intel_display *display)
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{
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/* Wa_22011091694:adlp */
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intel_de_rmw(display, GEN9_CLKGATE_DIS_5, 0, DPCE_GATING_DIS);
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/* Bspec/49189 Initialize Sequence */
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intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, DDI_CLOCK_REG_ACCESS, 0);
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}
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static void xe3plpd_display_wa_apply(struct intel_display *display)
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{
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/* Wa_22021451799 */
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intel_de_rmw(display, GEN9_CLKGATE_DIS_0, 0, DMG_GATING_DIS);
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}
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void intel_display_wa_apply(struct intel_display *display)
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{
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if (DISPLAY_VER(display) == 35)
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xe3plpd_display_wa_apply(display);
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else if (display->platform.alderlake_p)
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adlp_display_wa_apply(display);
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else if (DISPLAY_VER(display) == 12)
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xe_d_display_wa_apply(display);
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else if (DISPLAY_VER(display) == 11)
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gen11_display_wa_apply(display);
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}
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/*
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* Wa_16025573575:
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* Fixes: Issue with bitbashing on Xe3 based platforms.
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* Workaround: Set masks bits in GPIO CTL and preserve it during bitbashing sequence.
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*/
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static bool intel_display_needs_wa_16025573575(struct intel_display *display)
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{
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return DISPLAY_VERx100(display) == 3000 || DISPLAY_VERx100(display) == 3002 ||
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DISPLAY_VERx100(display) == 3500;
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}
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/*
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* Wa_14011503117:
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* Fixes: Before enabling the scaler DE fatal error is masked
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* Workaround: Unmask the DE fatal error register after enabling the scaler
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* and after waiting of at least 1 frame.
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*/
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bool __intel_display_wa(struct intel_display *display, enum intel_display_wa wa, const char *name)
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{
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switch (wa) {
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case INTEL_DISPLAY_WA_1409120013:
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return IS_DISPLAY_VER(display, 11, 12);
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case INTEL_DISPLAY_WA_1409767108:
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return (display->platform.alderlake_s ||
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(display->platform.rocketlake &&
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IS_DISPLAY_STEP(display, STEP_A0, STEP_B0)));
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case INTEL_DISPLAY_WA_13012396614:
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return DISPLAY_VERx100(display) == 3000 ||
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DISPLAY_VERx100(display) == 3500;
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case INTEL_DISPLAY_WA_14010477008:
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return display->platform.dg1 || display->platform.rocketlake ||
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(display->platform.tigerlake &&
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IS_DISPLAY_STEP(display, STEP_A0, STEP_D0));
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case INTEL_DISPLAY_WA_14010480278:
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return (IS_DISPLAY_VER(display, 10, 12));
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case INTEL_DISPLAY_WA_14010547955:
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return display->platform.dg2;
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case INTEL_DISPLAY_WA_14010685332:
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return INTEL_PCH_TYPE(display) >= PCH_CNP &&
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INTEL_PCH_TYPE(display) < PCH_DG1;
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case INTEL_DISPLAY_WA_14011294188:
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return INTEL_PCH_TYPE(display) >= PCH_TGP &&
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INTEL_PCH_TYPE(display) < PCH_DG1;
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case INTEL_DISPLAY_WA_14011503030:
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case INTEL_DISPLAY_WA_14011503117:
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case INTEL_DISPLAY_WA_22012358565:
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return DISPLAY_VER(display) == 13;
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case INTEL_DISPLAY_WA_14011508470:
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return (IS_DISPLAY_VERx100(display, 1200, 1300));
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case INTEL_DISPLAY_WA_14011765242:
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return display->platform.alderlake_s &&
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IS_DISPLAY_STEP(display, STEP_A0, STEP_A2);
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case INTEL_DISPLAY_WA_14014143976:
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return IS_DISPLAY_STEP(display, STEP_E0, STEP_FOREVER);
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case INTEL_DISPLAY_WA_14016740474:
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return IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_C0);
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case INTEL_DISPLAY_WA_14020863754:
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return DISPLAY_VERx100(display) == 3000 ||
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DISPLAY_VERx100(display) == 2000 ||
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DISPLAY_VERx100(display) == 1401;
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case INTEL_DISPLAY_WA_14025769978:
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return DISPLAY_VER(display) == 35;
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case INTEL_DISPLAY_WA_15013987218:
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return DISPLAY_VER(display) == 20;
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case INTEL_DISPLAY_WA_15018326506:
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return display->platform.battlemage;
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case INTEL_DISPLAY_WA_16011303918:
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case INTEL_DISPLAY_WA_22011320316:
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return display->platform.alderlake_p &&
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IS_DISPLAY_STEP(display, STEP_A0, STEP_B0);
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case INTEL_DISPLAY_WA_16011181250:
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return display->platform.rocketlake || display->platform.alderlake_s ||
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display->platform.dg2;
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case INTEL_DISPLAY_WA_16011342517:
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return display->platform.alderlake_p &&
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IS_DISPLAY_STEP(display, STEP_A0, STEP_D0);
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case INTEL_DISPLAY_WA_16011863758:
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return DISPLAY_VER(display) >= 11;
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case INTEL_DISPLAY_WA_16023588340:
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return intel_display_needs_wa_16023588340(display);
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case INTEL_DISPLAY_WA_16025573575:
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return intel_display_needs_wa_16025573575(display);
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case INTEL_DISPLAY_WA_16025596647:
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return DISPLAY_VER(display) == 20 &&
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IS_DISPLAY_VERx100_STEP(display, 3000,
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STEP_A0, STEP_B0);
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case INTEL_DISPLAY_WA_18034343758:
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return DISPLAY_VER(display) == 20 ||
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(display->platform.pantherlake &&
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IS_DISPLAY_STEP(display, STEP_A0, STEP_B0));
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case INTEL_DISPLAY_WA_22010178259:
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return DISPLAY_VER(display) == 12;
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case INTEL_DISPLAY_WA_22010947358:
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return display->platform.alderlake_p;
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case INTEL_DISPLAY_WA_22012278275:
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return display->platform.alderlake_p &&
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IS_DISPLAY_STEP(display, STEP_A0, STEP_E0);
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case INTEL_DISPLAY_WA_22014263786:
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return IS_DISPLAY_VERx100(display, 1100, 1400);
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case INTEL_DISPLAY_WA_22021048059:
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return IS_DISPLAY_VER(display, 14, 35);
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default:
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drm_WARN(display->drm, 1, "Missing Wa: %s\n", name);
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break;
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}
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return false;
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}
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