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ff854b32b6
The plan is to move all the mmio stuff into the display code itself.
As a first step implement the register polling in intel_de.c.
Currently i915 and xe implement this stuff in slightly different
ways, so there are some functional changes here. Try to go for a
reasonable middle ground between the i915 and xe implementations:
- the exponential backoff limit is the simpler approach taken
by i915 (== just clamp the max sleep duration to 1 ms)
- the fast vs. slow timeout handling is similar to i915 where
we first try the fast timeout and then again the slow timeout
if the condition still isn't satisfied. xe just adds up the
timeouts together, which is a bit weird.
- the atomic wait variant uses udelay() like xe, whereas i915
has no udelay()s in its atomic loop. As a compromise go for a
fixed 1 usec delay for short waits, instead of the somewhat
peculiar xe behaviour where it effectively just does one
iteration of the loop.
- keep the "use udelay() for < 10 usec waits" logic (which
more or less mirrors fsleep()), but include an explicit
might_sleep() even for these short waits when called from
a non-atomic intel_de_wait*() function. This should prevent
people from calling the non-atomic functions from the wrong
place.
Eventually we may want to switch over to poll_timeout*(),
but that lacks the exponential backoff, so a bit too
radical to change in one go.
v2: Initialize ret in intel_de_wait_for_register() to avoid a
warning from the compiler. This is actually a false positive
since we always have fast_timeout_us!=0 when slow_timeout_us!=0,
but the compiler can't see that
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patch.msgid.link/20260323094304.8171-1-ville.syrjala@linux.intel.com
179 lines
4.2 KiB
C
179 lines
4.2 KiB
C
// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2026 Intel Corporation
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*/
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#include <linux/delay.h>
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#include <drm/drm_print.h>
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#include "intel_de.h"
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static int __intel_de_wait_for_register(struct intel_display *display,
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i915_reg_t reg, u32 mask, u32 value,
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unsigned int timeout_us,
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u32 (*read)(struct intel_display *display, i915_reg_t reg),
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u32 *out_val, bool is_atomic)
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{
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const ktime_t end = ktime_add_us(ktime_get_raw(), timeout_us);
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int wait_max = 1000;
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int wait = 10;
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u32 reg_value;
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int ret;
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might_sleep_if(!is_atomic);
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if (timeout_us <= 10) {
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is_atomic = true;
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wait = 1;
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}
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for (;;) {
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bool expired = ktime_after(ktime_get_raw(), end);
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/* guarantee the condition is evaluated after timeout expired */
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barrier();
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reg_value = read(display, reg);
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if ((reg_value & mask) == value) {
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ret = 0;
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break;
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}
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if (expired) {
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ret = -ETIMEDOUT;
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break;
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}
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if (is_atomic)
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udelay(wait);
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else
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usleep_range(wait, wait << 1);
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if (wait < wait_max)
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wait <<= 1;
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}
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if (out_val)
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*out_val = reg_value;
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return ret;
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}
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static int intel_de_wait_for_register(struct intel_display *display,
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i915_reg_t reg, u32 mask, u32 value,
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unsigned int fast_timeout_us,
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unsigned int slow_timeout_us,
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u32 (*read)(struct intel_display *display, i915_reg_t reg),
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u32 *out_value, bool is_atomic)
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{
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int ret = -EINVAL;
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if (fast_timeout_us)
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ret = __intel_de_wait_for_register(display, reg, mask, value,
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fast_timeout_us, read,
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out_value, is_atomic);
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if (ret && slow_timeout_us)
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ret = __intel_de_wait_for_register(display, reg, mask, value,
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slow_timeout_us, read,
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out_value, is_atomic);
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return ret;
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}
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int intel_de_wait_us(struct intel_display *display, i915_reg_t reg,
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u32 mask, u32 value, unsigned int timeout_us,
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u32 *out_value)
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{
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int ret;
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intel_dmc_wl_get(display, reg);
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ret = intel_de_wait_for_register(display, reg, mask, value,
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timeout_us, 0,
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intel_de_read,
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out_value, false);
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intel_dmc_wl_put(display, reg);
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return ret;
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}
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int intel_de_wait_ms(struct intel_display *display, i915_reg_t reg,
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u32 mask, u32 value, unsigned int timeout_ms,
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u32 *out_value)
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{
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int ret;
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intel_dmc_wl_get(display, reg);
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ret = intel_de_wait_for_register(display, reg, mask, value,
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2, timeout_ms * 1000,
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intel_de_read,
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out_value, false);
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intel_dmc_wl_put(display, reg);
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return ret;
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}
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int intel_de_wait_fw_ms(struct intel_display *display, i915_reg_t reg,
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u32 mask, u32 value, unsigned int timeout_ms,
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u32 *out_value)
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{
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return intel_de_wait_for_register(display, reg, mask, value,
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2, timeout_ms * 1000,
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intel_de_read_fw,
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out_value, false);
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}
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int intel_de_wait_fw_us_atomic(struct intel_display *display, i915_reg_t reg,
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u32 mask, u32 value, unsigned int timeout_us,
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u32 *out_value)
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{
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return intel_de_wait_for_register(display, reg, mask, value,
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timeout_us, 0,
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intel_de_read_fw,
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out_value, true);
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}
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int intel_de_wait_for_set_us(struct intel_display *display, i915_reg_t reg,
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u32 mask, unsigned int timeout_us)
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{
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return intel_de_wait_us(display, reg, mask, mask, timeout_us, NULL);
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}
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int intel_de_wait_for_clear_us(struct intel_display *display, i915_reg_t reg,
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u32 mask, unsigned int timeout_us)
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{
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return intel_de_wait_us(display, reg, mask, 0, timeout_us, NULL);
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}
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int intel_de_wait_for_set_ms(struct intel_display *display, i915_reg_t reg,
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u32 mask, unsigned int timeout_ms)
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{
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return intel_de_wait_ms(display, reg, mask, mask, timeout_ms, NULL);
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}
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int intel_de_wait_for_clear_ms(struct intel_display *display, i915_reg_t reg,
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u32 mask, unsigned int timeout_ms)
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{
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return intel_de_wait_ms(display, reg, mask, 0, timeout_ms, NULL);
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}
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u8 intel_de_read8(struct intel_display *display, i915_reg_t reg)
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{
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/* this is only used on VGA registers (possible on pre-g4x) */
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drm_WARN_ON(display->drm, DISPLAY_VER(display) >= 5 || display->platform.g4x);
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return intel_uncore_read8(__to_uncore(display), reg);
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}
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void intel_de_write8(struct intel_display *display, i915_reg_t reg, u8 val)
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{
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drm_WARN_ON(display->drm, DISPLAY_VER(display) >= 5 || display->platform.g4x);
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intel_uncore_write8(__to_uncore(display), reg, val);
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}
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