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47a9050e67
Assign gpiochip_generic_config() to the set_config() callback to support pin configuration through the GPIO subsystem. This allows users to configure GPIO pin attributes like pull-up/down when specifying a GPIO line in the Device Tree. Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech> Reviewed-by: Anand Moon <linux.amoon@gmail.com> Acked-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Reviewed-by: Yixun Lan <dlan@kernel.org> Signed-off-by: Linus Walleij <linusw@kernel.org>
377 lines
10 KiB
C
377 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0 OR MIT
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/*
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* Copyright (C) 2023-2025 SpacemiT (Hangzhou) Technology Co. Ltd
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* Copyright (C) 2025 Yixun Lan <dlan@gentoo.org>
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*/
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#include <linux/clk.h>
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#include <linux/gpio/driver.h>
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#include <linux/gpio/generic.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/seq_file.h>
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#define SPACEMIT_NR_BANKS 4
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#define SPACEMIT_NR_GPIOS_PER_BANK 32
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#define to_spacemit_gpio_bank(x) container_of((x), struct spacemit_gpio_bank, gc)
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#define to_spacemit_gpio_regs(gb) ((gb)->sg->data->offsets)
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enum spacemit_gpio_registers {
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SPACEMIT_GPLR, /* port level - R */
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SPACEMIT_GPDR, /* port direction - R/W */
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SPACEMIT_GPSR, /* port set - W */
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SPACEMIT_GPCR, /* port clear - W */
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SPACEMIT_GRER, /* port rising edge R/W */
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SPACEMIT_GFER, /* port falling edge R/W */
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SPACEMIT_GEDR, /* edge detect status - R/W1C */
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SPACEMIT_GSDR, /* (set) direction - W */
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SPACEMIT_GCDR, /* (clear) direction - W */
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SPACEMIT_GSRER, /* (set) rising edge detect enable - W */
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SPACEMIT_GCRER, /* (clear) rising edge detect enable - W */
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SPACEMIT_GSFER, /* (set) falling edge detect enable - W */
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SPACEMIT_GCFER, /* (clear) falling edge detect enable - W */
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SPACEMIT_GAPMASK, /* interrupt mask , 0 disable, 1 enable - R/W */
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SPACEMIT_GCPMASK, /* interrupt mask for K3 */
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};
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struct spacemit_gpio;
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struct spacemit_gpio_data {
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const unsigned int *offsets;
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u32 bank_offsets[SPACEMIT_NR_BANKS];
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};
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struct spacemit_gpio_bank {
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struct gpio_generic_chip chip;
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struct spacemit_gpio *sg;
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void __iomem *base;
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u32 irq_mask;
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u32 irq_rising_edge;
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u32 irq_falling_edge;
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};
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struct spacemit_gpio {
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struct device *dev;
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const struct spacemit_gpio_data *data;
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struct spacemit_gpio_bank sgb[SPACEMIT_NR_BANKS];
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};
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static u32 spacemit_gpio_read(struct spacemit_gpio_bank *gb,
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enum spacemit_gpio_registers reg)
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{
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return readl(gb->base + to_spacemit_gpio_regs(gb)[reg]);
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}
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static void spacemit_gpio_write(struct spacemit_gpio_bank *gb,
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enum spacemit_gpio_registers reg, u32 val)
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{
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writel(val, gb->base + to_spacemit_gpio_regs(gb)[reg]);
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}
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static u32 spacemit_gpio_bank_index(struct spacemit_gpio_bank *gb)
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{
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return (u32)(gb - gb->sg->sgb);
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}
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static irqreturn_t spacemit_gpio_irq_handler(int irq, void *dev_id)
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{
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struct spacemit_gpio_bank *gb = dev_id;
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unsigned long pending;
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u32 n, gedr;
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gedr = spacemit_gpio_read(gb, SPACEMIT_GEDR);
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if (!gedr)
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return IRQ_NONE;
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spacemit_gpio_write(gb, SPACEMIT_GEDR, gedr);
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pending = gedr & gb->irq_mask;
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if (!pending)
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return IRQ_NONE;
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for_each_set_bit(n, &pending, BITS_PER_LONG)
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handle_nested_irq(irq_find_mapping(gb->chip.gc.irq.domain, n));
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return IRQ_HANDLED;
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}
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static void spacemit_gpio_irq_ack(struct irq_data *d)
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{
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struct spacemit_gpio_bank *gb = irq_data_get_irq_chip_data(d);
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spacemit_gpio_write(gb, SPACEMIT_GEDR, BIT(irqd_to_hwirq(d)));
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}
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static void spacemit_gpio_irq_mask(struct irq_data *d)
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{
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struct spacemit_gpio_bank *gb = irq_data_get_irq_chip_data(d);
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u32 bit = BIT(irqd_to_hwirq(d));
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gb->irq_mask &= ~bit;
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spacemit_gpio_write(gb, SPACEMIT_GAPMASK, gb->irq_mask);
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if (bit & gb->irq_rising_edge)
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spacemit_gpio_write(gb, SPACEMIT_GCRER, bit);
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if (bit & gb->irq_falling_edge)
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spacemit_gpio_write(gb, SPACEMIT_GCFER, bit);
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}
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static void spacemit_gpio_irq_unmask(struct irq_data *d)
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{
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struct spacemit_gpio_bank *gb = irq_data_get_irq_chip_data(d);
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u32 bit = BIT(irqd_to_hwirq(d));
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gb->irq_mask |= bit;
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if (bit & gb->irq_rising_edge)
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spacemit_gpio_write(gb, SPACEMIT_GSRER, bit);
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if (bit & gb->irq_falling_edge)
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spacemit_gpio_write(gb, SPACEMIT_GSFER, bit);
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spacemit_gpio_write(gb, SPACEMIT_GAPMASK, gb->irq_mask);
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}
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static int spacemit_gpio_irq_set_type(struct irq_data *d, unsigned int type)
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{
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struct spacemit_gpio_bank *gb = irq_data_get_irq_chip_data(d);
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u32 bit = BIT(irqd_to_hwirq(d));
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if (type & IRQ_TYPE_EDGE_RISING) {
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gb->irq_rising_edge |= bit;
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spacemit_gpio_write(gb, SPACEMIT_GSRER, bit);
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} else {
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gb->irq_rising_edge &= ~bit;
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spacemit_gpio_write(gb, SPACEMIT_GCRER, bit);
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}
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if (type & IRQ_TYPE_EDGE_FALLING) {
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gb->irq_falling_edge |= bit;
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spacemit_gpio_write(gb, SPACEMIT_GSFER, bit);
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} else {
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gb->irq_falling_edge &= ~bit;
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spacemit_gpio_write(gb, SPACEMIT_GCFER, bit);
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}
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return 0;
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}
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static void spacemit_gpio_irq_print_chip(struct irq_data *data, struct seq_file *p)
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{
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struct spacemit_gpio_bank *gb = irq_data_get_irq_chip_data(data);
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seq_printf(p, "%s-%d", dev_name(gb->chip.gc.parent), spacemit_gpio_bank_index(gb));
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}
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static struct irq_chip spacemit_gpio_chip = {
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.name = "k1-gpio-irqchip",
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.irq_ack = spacemit_gpio_irq_ack,
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.irq_mask = spacemit_gpio_irq_mask,
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.irq_unmask = spacemit_gpio_irq_unmask,
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.irq_set_type = spacemit_gpio_irq_set_type,
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.irq_print_chip = spacemit_gpio_irq_print_chip,
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.flags = IRQCHIP_IMMUTABLE | IRQCHIP_SKIP_SET_WAKE,
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GPIOCHIP_IRQ_RESOURCE_HELPERS,
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};
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static bool spacemit_of_node_instance_match(struct gpio_chip *gc, unsigned int i)
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{
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struct spacemit_gpio_bank *gb = gpiochip_get_data(gc);
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struct spacemit_gpio *sg = gb->sg;
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if (i >= SPACEMIT_NR_BANKS)
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return false;
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return (gc == &sg->sgb[i].chip.gc);
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}
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static int spacemit_gpio_add_bank(struct spacemit_gpio *sg,
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void __iomem *regs,
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int index, int irq)
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{
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struct spacemit_gpio_bank *gb = &sg->sgb[index];
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struct gpio_generic_chip_config config;
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struct gpio_chip *gc = &gb->chip.gc;
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struct device *dev = sg->dev;
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struct gpio_irq_chip *girq;
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void __iomem *dat, *set, *clr, *dirout;
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int ret;
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gb->base = regs + sg->data->bank_offsets[index];
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gb->sg = sg;
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dat = gb->base + to_spacemit_gpio_regs(gb)[SPACEMIT_GPLR];
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set = gb->base + to_spacemit_gpio_regs(gb)[SPACEMIT_GPSR];
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clr = gb->base + to_spacemit_gpio_regs(gb)[SPACEMIT_GPCR];
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dirout = gb->base + to_spacemit_gpio_regs(gb)[SPACEMIT_GPDR];
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config = (struct gpio_generic_chip_config) {
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.dev = dev,
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.sz = 4,
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.dat = dat,
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.set = set,
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.clr = clr,
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.dirout = dirout,
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.flags = GPIO_GENERIC_UNREADABLE_REG_SET,
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};
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/* This registers 32 GPIO lines per bank */
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ret = gpio_generic_chip_init(&gb->chip, &config);
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if (ret)
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return dev_err_probe(dev, ret, "failed to init gpio chip\n");
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gc->label = dev_name(dev);
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gc->request = gpiochip_generic_request;
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gc->free = gpiochip_generic_free;
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gc->set_config = gpiochip_generic_config;
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gc->ngpio = SPACEMIT_NR_GPIOS_PER_BANK;
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gc->base = -1;
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gc->of_gpio_n_cells = 3;
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gc->of_node_instance_match = spacemit_of_node_instance_match;
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girq = &gc->irq;
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girq->threaded = true;
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girq->handler = handle_simple_irq;
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gpio_irq_chip_set_chip(girq, &spacemit_gpio_chip);
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/* Disable Interrupt */
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spacemit_gpio_write(gb, SPACEMIT_GAPMASK, 0);
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/* Disable Edge Detection Settings */
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spacemit_gpio_write(gb, SPACEMIT_GRER, 0x0);
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spacemit_gpio_write(gb, SPACEMIT_GFER, 0x0);
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/* Clear Interrupt */
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spacemit_gpio_write(gb, SPACEMIT_GCRER, 0xffffffff);
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spacemit_gpio_write(gb, SPACEMIT_GCFER, 0xffffffff);
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ret = devm_request_threaded_irq(dev, irq, NULL,
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spacemit_gpio_irq_handler,
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IRQF_ONESHOT | IRQF_SHARED,
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gb->chip.gc.label, gb);
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if (ret < 0)
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return dev_err_probe(dev, ret, "failed to register IRQ\n");
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ret = devm_gpiochip_add_data(dev, gc, gb);
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if (ret)
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return ret;
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/* Distuingish IRQ domain, for selecting threecells mode */
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irq_domain_update_bus_token(girq->domain, DOMAIN_BUS_WIRED);
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return 0;
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}
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static int spacemit_gpio_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct spacemit_gpio *sg;
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struct clk *core_clk, *bus_clk;
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void __iomem *regs;
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int i, irq, ret;
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sg = devm_kzalloc(dev, sizeof(*sg), GFP_KERNEL);
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if (!sg)
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return -ENOMEM;
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sg->data = of_device_get_match_data(dev);
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if (!sg->data)
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return dev_err_probe(dev, -EINVAL, "No available compatible data.");
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regs = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(regs))
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return PTR_ERR(regs);
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irq = platform_get_irq(pdev, 0);
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if (irq < 0)
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return irq;
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sg->dev = dev;
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core_clk = devm_clk_get_enabled(dev, "core");
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if (IS_ERR(core_clk))
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return dev_err_probe(dev, PTR_ERR(core_clk), "failed to get clock\n");
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bus_clk = devm_clk_get_enabled(dev, "bus");
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if (IS_ERR(bus_clk))
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return dev_err_probe(dev, PTR_ERR(bus_clk), "failed to get bus clock\n");
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for (i = 0; i < SPACEMIT_NR_BANKS; i++) {
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ret = spacemit_gpio_add_bank(sg, regs, i, irq);
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if (ret)
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return ret;
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}
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return 0;
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}
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static const unsigned int spacemit_gpio_k1_offsets[] = {
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[SPACEMIT_GPLR] = 0x00,
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[SPACEMIT_GPDR] = 0x0c,
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[SPACEMIT_GPSR] = 0x18,
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[SPACEMIT_GPCR] = 0x24,
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[SPACEMIT_GRER] = 0x30,
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[SPACEMIT_GFER] = 0x3c,
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[SPACEMIT_GEDR] = 0x48,
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[SPACEMIT_GSDR] = 0x54,
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[SPACEMIT_GCDR] = 0x60,
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[SPACEMIT_GSRER] = 0x6c,
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[SPACEMIT_GCRER] = 0x78,
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[SPACEMIT_GSFER] = 0x84,
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[SPACEMIT_GCFER] = 0x90,
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[SPACEMIT_GAPMASK] = 0x9c,
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[SPACEMIT_GCPMASK] = 0xA8,
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};
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static const unsigned int spacemit_gpio_k3_offsets[] = {
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[SPACEMIT_GPLR] = 0x0,
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[SPACEMIT_GPDR] = 0x4,
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[SPACEMIT_GPSR] = 0x8,
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[SPACEMIT_GPCR] = 0xc,
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[SPACEMIT_GRER] = 0x10,
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[SPACEMIT_GFER] = 0x14,
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[SPACEMIT_GEDR] = 0x18,
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[SPACEMIT_GSDR] = 0x1c,
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[SPACEMIT_GCDR] = 0x20,
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[SPACEMIT_GSRER] = 0x24,
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[SPACEMIT_GCRER] = 0x28,
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[SPACEMIT_GSFER] = 0x2c,
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[SPACEMIT_GCFER] = 0x30,
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[SPACEMIT_GAPMASK] = 0x34,
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[SPACEMIT_GCPMASK] = 0x38,
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};
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static const struct spacemit_gpio_data k1_gpio_data = {
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.offsets = spacemit_gpio_k1_offsets,
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.bank_offsets = { 0x0, 0x4, 0x8, 0x100 },
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};
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static const struct spacemit_gpio_data k3_gpio_data = {
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.offsets = spacemit_gpio_k3_offsets,
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.bank_offsets = { 0x0, 0x40, 0x80, 0x100 },
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};
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static const struct of_device_id spacemit_gpio_dt_ids[] = {
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{ .compatible = "spacemit,k1-gpio", .data = &k1_gpio_data },
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{ .compatible = "spacemit,k3-gpio", .data = &k3_gpio_data },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, spacemit_gpio_dt_ids);
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static struct platform_driver spacemit_gpio_driver = {
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.probe = spacemit_gpio_probe,
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.driver = {
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.name = "spacemit-gpio",
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.of_match_table = spacemit_gpio_dt_ids,
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},
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};
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module_platform_driver(spacemit_gpio_driver);
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MODULE_AUTHOR("Yixun Lan <dlan@gentoo.org>");
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MODULE_DESCRIPTION("GPIO driver for SpacemiT K1/K3 SoC");
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MODULE_LICENSE("GPL");
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