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804b10deb0
Here's various improvements and fixes for the clk subsystem that was posted prior to the opening of the last merge window. - Add spread spectrum clock (SSC) support to the clk framework, including a new assigned-clock-sscs devicetree property and clk_hw_set_spread_spectrum() API with KUnit tests (Peng Fan) - Add SCMI clock OEM extensions for the i.MX95 clock driver and introduce a common SCMI clock header (Peng Fan) - Add clock, reset, and devicetree bindings for the ESWIN EIC7700 HSP clock and reset generator (Xuyang Dong) - Add clk_determine_rate_noop() helper for clock drivers that can do any rate, and convert existing open-coded implementations across hisilicon, imx, qcom, renesas, rp1, samsung, scpi, sprd, mediatek phy, and mediatek pmdomain drivers (Brian Masney) - Add kernel-doc documentation for struct clk_core and the core clock flags, and wire up clk identifiers into the documentation build (Brian Masney) - Fix clk_divider_bestdiv() returning the minimum rate instead of the maximum rate for large rate requests, with KUnit tests (Lad Prabhakar) - Fix Nuvoton MA35D1 PLL frequency calculation including ignored div_u64 return values, incorrect PLL_CTL1_FRAC bit field width, and broken determine_rate logic (Joey Lu) - Support unique clock names for multi-socket Tegra platforms (Jon Hunter) - Allow COMPILE_TEST builds for HiSilicon clock drivers (Rosen Penev) - Various fixes and cleanups from Akari Tsuyukusa, Alexander A. Klimov, Brian Masney, David Carlier, David Laight, Min zhang, Myeonghun Pak, Pavel Löbl, Randy Dunlap, Rob Herring, Rosen Penev, Uwe Kleine-König, William Theesfeld, Xuyang Dong, and Yu-Chun Lin Signed-off-by: Brian Masney <bmasney@redhat.com> -----BEGIN PGP SIGNATURE----- iIwEABYKADQWIQSkbTJwWGWqPd7cKQS30t0nXX7AhwUCakLuwRYcbWFzbmV5YkBv bnN0YXRpb24ub3JnAAoJELfS3SddfsCH1qIA/3OYdBm1fIrd/PumuFj/6xnito0J nwY64dzlOm4kPVynAQDGDUxQMevRq8AFXh33kOh+cCFg7H9CXjF55ajB2TXaBg== =1BFM -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQJIBAABCAAyFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAmqDNnUUHHN3Ym95ZEBj aHJvbWl1bS5vcmcACgkQrQKIl8bklSU1oxAAiKegvy9n27Avul9t7GX9SYpyM93E XXvr3kdI6ySTkAk/CXqSUKLS0FnqMepQE6b1FSiRQGOyPl0iYxXFKZ3iwd5ZHHIN AWWwXYhzAuwOXNnNzlz3SFJ40lt8zTLY4Y20sG3/+iuIiqotywONWqr1JlUwlgVI ahmGqWPj2qtuKCnxnOQnBNcaA/xd3NqdjHt0W1UgXP9Hn9j0l+EhL7f4TJVp4Wq5 LU+jlA7g6Btxy5JrJOpzdgd84bPNw4xxYOhzn3ek8ULB5H0QRj36cu2ZahNudZJF ObIr23OOgRJLZtKQ/WlM5fHXONuhnE9CSTiBEeXSr2yon0JKcJ8bjKUvTilJhZ34 TV5DSBxB70E0Vs4omJJ0NtKsJWW+zoa53yU2mT88VWQNTDLfTe4VHVbBCBN9cBnV aS8ssQF9uipsOKEGQ1aQG9neV2ML0OXd3nMx9f8VgMcfV5K8Wbtt5oRFtQtl5fS/ uCkTbII+IL29MMVJ6+X3sRilFY8SsKxaG1gDmk50LwcMUVx4hzNGOhQC/1TPRNG2 ZuSEeRX10syBwI5txupnxD1mJClw2ZxE9QmSTmKmWI1Y3aSdcSdtKnEobhLXJmmS 7PFtOe9Rf8lRbYKxZGaW63R/9fOmrf3wyG9kzepLKJl8loV7SRJ8by6psNBfBgVO kyANlk/27dpi1Zo= =QbCr -----END PGP SIGNATURE----- Merge tag 'clk-misc-for-v7.3' of ssh://github.com/masneyb/linux into clk-pile Pull clk patches picked up by Brian Masney: Here's various improvements and fixes for the clk subsystem that was posted prior to the opening of the last merge window. - Add spread spectrum clock (SSC) support to the clk framework, including a new assigned-clock-sscs devicetree property and clk_hw_set_spread_spectrum() API with KUnit tests (Peng Fan) - Add SCMI clock OEM extensions for the i.MX95 clock driver and introduce a common SCMI clock header (Peng Fan) - Add clock, reset, and devicetree bindings for the ESWIN EIC7700 HSP clock and reset generator (Xuyang Dong) - Add clk_determine_rate_noop() helper for clock drivers that can do any rate, and convert existing open-coded implementations across hisilicon, imx, qcom, renesas, rp1, samsung, scpi, sprd, mediatek phy, and mediatek pmdomain drivers (Brian Masney) - Add kernel-doc documentation for struct clk_core and the core clock flags, and wire up clk identifiers into the documentation build (Brian Masney) - Fix clk_divider_bestdiv() returning the minimum rate instead of the maximum rate for large rate requests, with KUnit tests (Lad Prabhakar) - Fix Nuvoton MA35D1 PLL frequency calculation including ignored div_u64 return values, incorrect PLL_CTL1_FRAC bit field width, and broken determine_rate logic (Joey Lu) - Support unique clock names for multi-socket Tegra platforms (Jon Hunter) - Allow COMPILE_TEST builds for HiSilicon clock drivers (Rosen Penev) - Various fixes and cleanups from Akari Tsuyukusa, Alexander A. Klimov, Brian Masney, David Carlier, David Laight, Min zhang, Myeonghun Pak, Pavel Löbl, Randy Dunlap, Rob Herring, Rosen Penev, Uwe Kleine-König, William Theesfeld, Xuyang Dong, and Yu-Chun Lin Signed-off-by: Brian Masney <bmasney@redhat.com> [sboyd@kernel.org: Fix allmodconfig modpost failure in scmi] * tag 'clk-misc-for-v7.3' of ssh://github.com/masneyb/linux: (53 commits) pmdomain: mediatek: mtk-mfg: use clk_determine_rate_noop() pmdomain: mediatek: airoha: use clk_determine_rate_noop() phy: mediatek: phy-mtk-hdmi-mt2701: use clk_determine_rate_noop() clk: sprd: use clk_determine_rate_noop() clk: scpi: use clk_determine_rate_noop() clk: samsung: acpm: use clk_determine_rate_noop() clk: rp1: use clk_determine_rate_noop() clk: renesas: rzg2l-cpg: use clk_determine_rate_noop() clk: qcom: smd-rpm: use clk_determine_rate_noop() clk: qcom: rpmh: use clk_determine_rate_noop() clk: qcom: rpm: use clk_determine_rate_noop() clk: imx: scu: use clk_determine_rate_noop() clk: hisilicon: hi3660-stub: use clk_determine_rate_noop() clk: add clk_determine_rate_noop() clk: imx: scu: drop redundant init.ops variable assignment clk: test: convert constants to use HZ_PER_MHZ docs: clk: include some identifiers to keep documentation up to date clk: add kernel docs for struct clk_core clk: add kernel docs for the core flags clk: hisilicon: allow COMPILE_TEST builds ... |
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| .. | ||
| common.c | ||
| common.h | ||
| composite.c | ||
| composite.h | ||
| div.c | ||
| div.h | ||
| gate.c | ||
| gate.h | ||
| Kconfig | ||
| Makefile | ||
| mux.c | ||
| mux.h | ||
| pll.c | ||
| pll.h | ||
| sc9860-clk.c | ||
| sc9863a-clk.c | ||
| ums512-clk.c | ||