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data fixes for things that weren't used yet. One thing that's new here in the core is SSC spread spectrum support (SSC) in the clk provider API. The idea is that DT authors will configure SSC for certain clks and they'll be configured at clk provider registration time or when a consumer device is probed, similar to how we handle assigned clk rates or parents. On the clk driver side we have Qualcomm adding almost half the diff because they add support for 4 different SoCs and then a long tail of other SoCs like Mediatek, Renesas, Rockchip, SpaceMiT, etc. add more SoC support this time around. Luckily it's mostly clk data for these new SoCs because the actual clk_ops are already there. Beyond the new drivers we get all the little fixups for more compilation coverage or usage of more modern APIs. That all looks normal. Finally, I kinda buried the lead, I'm bringing on Brian and Jerome to help out with maintaining the clk subsystem. The current working model is already semi-distributed in that silicon vendors typically take care of their drivers and send me pull requests but I'm becoming a bottleneck for new drivers and core framework review because this has become a 100% volunteer effort on my part. Mike is stepping down after all these years (thanks Mike!) and that jump started the conversation around finding co-maintainers. Brian and Jerome have graciously offered to help me with the work load, meaning in the future they'll be sending pull requests and committing directly to the clk.git tree. They've both been around on the list for a while, I've met them both in person, and they've been making changes to the core clk framework along with helping review patches so I'm pretty confident this will work well. Core: - devm_clk_bulk_get_enable() consumer API - devm_clk_hw_register_composite_pdata() provider API - Spread Spectrum Clock (SSC) support via DT bindings and provider APIs - Divider clk rounding improved (and tested) New Drivers: - Cix Sky1 audio subsystem (AUDSS) - UltraRISC DP1000 - MediaTek MT8173 MFG_TOP - Si549 - Aspeed AST2700 PECI - Airoha EN7523 PCIe - Rockchip RV1106 - Mobileye EyeQ7H - Qualcomm Maili GCC, TCSR, RPMh, and video clks - Qualcomm Shikra GCC, RPM, GPU, display, and audio clks - Qualcomm Nord display and graphics clks - Qualcomm Glymur camera and EVA clks - Qualcomm Hawi video clks - Amlogic A9 AO and peripheral clks - Renesas R-Car X5H (R8A78000) CPG -----BEGIN PGP SIGNATURE----- iQJIBAABCAAyFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAmqPGK4UHHN3Ym95ZEBj aHJvbWl1bS5vcmcACgkQrQKIl8bklSXB+g/+O8McZyE7kqNPiz8nQNQq9YwzO9uB /5LkNUUvvxhzJ9YEcXx8HCkmUcAks+kMCHzrZ/gxAN6BQGv9qrTChZZD2ZmD8e50 nj3IxyvN51PwRk5ley1PEsUILrnOqRpY6g83arnFppTP2aU/NxFFGjc5u+5qlIT4 f0xj2sJ0H96Ykw+brSJgEj9MXJHMEKerEqBmaDd0boHavDV3YkT/HxRrjy3WH/sE FBAdq6sOAEX3qnNwsF9debrfg1nKJGH2U8ecb1JThlAufn8yHvC+mxr3P4USxdov xGhDkvKbS+9nkbxeL1LOhnoReOWqNBGQg9qmadQKTrPEu/BAOb8nG62xpucIgLSl 6X3AACRzEE8u8Thaboz+cvQluQfOo667xz5X+bpTsQjfQuq4Yh0F4pO6pLmLd+LT NdOzbQctglbpwHbXIxXQftg+Fnk1bgERILW64DU9mUqXzSJJG9uzv+Ne5R0TTXJp TMRTp/o8o4Fclr1WB73wES523xpf7VltPfUw5XL9UN2xCCY5TI2bpHQwgfmkz/6J nHmxNBBK19qlNFzDovN1gfgwn9XVDLmT7YVSw0El24kINHs7rYXuGc++OX+LmUb3 r19QxJXU8ESV89ZGJYhnaSOKrCj1d4W49AkVqovvJXXYxxlFTab1ox8xKnhUlxGH SGDC+kZah2zUl7A= =iYa8 -----END PGP SIGNATURE----- Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "Mostly the usual clk driver updates and new SoC additions plus non-critical data fixes for things that weren't used yet. One thing that's new here in the core is SSC spread spectrum support (SSC) in the clk provider API. The idea is that DT authors will configure SSC for certain clks and they'll be configured at clk provider registration time or when a consumer device is probed, similar to how we handle assigned clk rates or parents. On the clk driver side we have Qualcomm adding almost half the diff because they add support for 4 different SoCs and then a long tail of other SoCs like Mediatek, Renesas, Rockchip, SpaceMiT, etc. add more SoC support this time around. Luckily it's mostly clk data for these new SoCs because the actual clk_ops are already there. Beyond the new drivers we get all the little fixups for more compilation coverage or usage of more modern APIs. That all looks normal. Finally, I kinda buried the lede, I'm bringing on Brian and Jerome to help out with maintaining the clk subsystem. The current working model is already semi-distributed in that silicon vendors typically take care of their drivers and send me pull requests but I'm becoming a bottleneck for new drivers and core framework review because this has become a 100% volunteer effort on my part. Mike is stepping down after all these years (thanks Mike!) and that jump started the conversation around finding co-maintainers. Brian and Jerome have graciously offered to help me with the work load, meaning in the future they'll be sending pull requests and committing directly to the clk.git tree. They've both been around on the list for a while, I've met them both in person, and they've been making changes to the core clk framework along with helping review patches so I'm pretty confident this will work well. Core: - devm_clk_bulk_get_enable() consumer API - devm_clk_hw_register_composite_pdata() provider API - Spread Spectrum Clock (SSC) support via DT bindings and provider APIs - Divider clk rounding improved (and tested) New Drivers: - Cix Sky1 audio subsystem (AUDSS) - UltraRISC DP1000 - MediaTek MT8173 MFG_TOP - Si549 - Aspeed AST2700 PECI - Airoha EN7523 PCIe - Rockchip RV1106 - Mobileye EyeQ7H - Qualcomm Maili GCC, TCSR, RPMh, and video clks - Qualcomm Shikra GCC, RPM, GPU, display, and audio clks - Qualcomm Nord display and graphics clks - Qualcomm Glymur camera and EVA clks - Qualcomm Hawi video clks - Amlogic A9 AO and peripheral clks - Renesas R-Car X5H (R8A78000) CPG" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (269 commits) clk: microchip: mpfs: fix regmap_update_bits() mask/val order clk: visconti: Make sure clk_init_data is fully initialized clk: ti: Make sure clk_init_data is fully initialized MAINTAINERS: Add Brian Masney and Jerome Brunet as co-maintainers for clk subsystem Drop Michael Turquette's clk maintainer entry clk: ti: composite: resolve parent clocks by DT index, not by name clk: ti: mux: resolve parent clocks by DT index, not by name clk: devres: fix cleanup in devm_clk_get_optional_enabled_with_rate() dt-bindings: clock: ti,keystone-gate: Convert to DT schema dt-bindings: clock: ti: Convert APLL clock to DT schema clk: zynq: pll: Fix kernel-doc after determine_rate() conversion dt-bindings: clock: ti,clockdomain: Convert to DT schema dt-bindings: clock: Correct white-space style clk: samsung: Don't include <linux/mod_devicetable.h> clk: at91: Read "reg" with helper clk: renesas: Add R-Car X5H CPG driver clk: rockchip: rk3576: fix source muxes for SPI0..SPI4 clk: rockchip: Add clock controller for the RV1106 dt-bindings: clock: rockchip: Add RV1106 CRU support dt-bindings: clock: Document Renesas R-Car X5H Clock Pulse Generator ... |
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|---|---|---|
| .. | ||
| clk-cpu.c | ||
| clk-ddr.c | ||
| clk-gate-grf.c | ||
| clk-half-divider.c | ||
| clk-inverter.c | ||
| clk-mmc-phase.c | ||
| clk-muxgrf.c | ||
| clk-pll.c | ||
| clk-px30.c | ||
| clk-rk3036.c | ||
| clk-rk3128.c | ||
| clk-rk3188.c | ||
| clk-rk3228.c | ||
| clk-rk3288.c | ||
| clk-rk3308.c | ||
| clk-rk3328.c | ||
| clk-rk3368.c | ||
| clk-rk3399.c | ||
| clk-rk3506.c | ||
| clk-rk3528.c | ||
| clk-rk3562.c | ||
| clk-rk3568.c | ||
| clk-rk3576.c | ||
| clk-rk3588.c | ||
| clk-rv1103b.c | ||
| clk-rv1106.c | ||
| clk-rv1108.c | ||
| clk-rv1126.c | ||
| clk-rv1126b.c | ||
| clk.c | ||
| clk.h | ||
| gate-link.c | ||
| Kconfig | ||
| Makefile | ||
| rst-rk3506.c | ||
| rst-rk3528.c | ||
| rst-rk3562.c | ||
| rst-rk3576.c | ||
| rst-rk3588.c | ||
| rst-rv1126b.c | ||
| softrst.c | ||