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778149217d
Add support for Qualcomm Maili video clock controller driver for video clients to be able to request for videocc clocks. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com> Signed-off-by: Jagadeesh Kona <jagadeesh.kona@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260717-maili_videocc-v3-2-6656694b06a7@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
661 lines
17 KiB
C
661 lines
17 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
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*/
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <dt-bindings/clock/qcom,maili-videocc.h>
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#include "clk-alpha-pll.h"
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#include "clk-branch.h"
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#include "clk-rcg.h"
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#include "clk-regmap.h"
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#include "clk-regmap-divider.h"
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#include "common.h"
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#include "gdsc.h"
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#include "reset.h"
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#define ACCU_CFG_MASK GENMASK(25, 21)
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enum {
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DT_BI_TCXO,
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DT_AHB_CLK,
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};
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enum {
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P_BI_TCXO,
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P_VIDEO_CC_PLL0_OUT_MAIN,
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P_VIDEO_CC_PLL1_OUT_MAIN,
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P_VIDEO_CC_PLL2_OUT_MAIN,
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};
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static const struct pll_vco taycan_eha_t_vco[] = {
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{ 249600000, 2500000000, 0 },
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};
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/* 360.0 MHz Configuration */
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static const struct alpha_pll_config video_cc_pll0_config = {
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.l = 0x12,
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.cal_l = 0x42,
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.alpha = 0xc000,
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.config_ctl_val = 0xa5c400e7,
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.config_ctl_hi_val = 0x0a806160,
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.config_ctl_hi1_val = 0xf51dea20,
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.user_ctl_val = 0x00000000,
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.user_ctl_hi_val = 0x00000002,
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};
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static struct clk_alpha_pll video_cc_pll0 = {
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.offset = 0x0,
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.config = &video_cc_pll0_config,
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.vco_table = taycan_eha_t_vco,
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.num_vco = ARRAY_SIZE(taycan_eha_t_vco),
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EHA_T],
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.clkr = {
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.hw.init = &(const struct clk_init_data) {
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.name = "video_cc_pll0",
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.parent_data = &(const struct clk_parent_data) {
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.index = DT_BI_TCXO,
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},
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.num_parents = 1,
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.ops = &clk_alpha_pll_taycan_eha_t_ops,
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},
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},
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};
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/* 480.0 MHz Configuration */
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static const struct alpha_pll_config video_cc_pll1_config = {
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.l = 0x19,
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.cal_l = 0x42,
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.alpha = 0x0,
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.config_ctl_val = 0xa5c400e7,
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.config_ctl_hi_val = 0x0a806160,
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.config_ctl_hi1_val = 0xf51dea20,
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.user_ctl_val = 0x00000000,
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.user_ctl_hi_val = 0x00000002,
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};
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static struct clk_alpha_pll video_cc_pll1 = {
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.offset = 0x1000,
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.config = &video_cc_pll1_config,
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.vco_table = taycan_eha_t_vco,
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.num_vco = ARRAY_SIZE(taycan_eha_t_vco),
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EHA_T],
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.clkr = {
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.hw.init = &(const struct clk_init_data) {
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.name = "video_cc_pll1",
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.parent_data = &(const struct clk_parent_data) {
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.index = DT_BI_TCXO,
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},
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.num_parents = 1,
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.ops = &clk_alpha_pll_taycan_eha_t_ops,
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},
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},
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};
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/* 480.0 MHz Configuration */
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static const struct alpha_pll_config video_cc_pll2_config = {
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.l = 0x19,
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.cal_l = 0x42,
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.alpha = 0x0,
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.config_ctl_val = 0xa5c400e7,
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.config_ctl_hi_val = 0x0a806160,
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.config_ctl_hi1_val = 0xf51dea20,
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.user_ctl_val = 0x00000000,
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.user_ctl_hi_val = 0x00000002,
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};
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static struct clk_alpha_pll video_cc_pll2 = {
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.offset = 0x2000,
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.config = &video_cc_pll2_config,
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.vco_table = taycan_eha_t_vco,
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.num_vco = ARRAY_SIZE(taycan_eha_t_vco),
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EHA_T],
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.clkr = {
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.hw.init = &(const struct clk_init_data) {
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.name = "video_cc_pll2",
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.parent_data = &(const struct clk_parent_data) {
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.index = DT_BI_TCXO,
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},
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.num_parents = 1,
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.ops = &clk_alpha_pll_taycan_eha_t_ops,
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},
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},
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};
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static const struct parent_map video_cc_parent_map_0[] = {
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{ P_BI_TCXO, 0 },
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};
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static const struct clk_parent_data video_cc_parent_data_0[] = {
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{ .index = DT_BI_TCXO },
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};
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static const struct parent_map video_cc_parent_map_1[] = {
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{ P_BI_TCXO, 0 },
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{ P_VIDEO_CC_PLL1_OUT_MAIN, 1 },
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};
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static const struct clk_parent_data video_cc_parent_data_1[] = {
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{ .index = DT_BI_TCXO },
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{ .hw = &video_cc_pll1.clkr.hw },
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};
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static const struct parent_map video_cc_parent_map_2[] = {
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{ P_BI_TCXO, 0 },
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{ P_VIDEO_CC_PLL2_OUT_MAIN, 1 },
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};
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static const struct clk_parent_data video_cc_parent_data_2[] = {
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{ .index = DT_BI_TCXO },
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{ .hw = &video_cc_pll2.clkr.hw },
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};
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static const struct parent_map video_cc_parent_map_3[] = {
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{ P_BI_TCXO, 0 },
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{ P_VIDEO_CC_PLL0_OUT_MAIN, 1 },
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};
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static const struct clk_parent_data video_cc_parent_data_3[] = {
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{ .index = DT_BI_TCXO },
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{ .hw = &video_cc_pll0.clkr.hw },
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};
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static const struct freq_tbl ftbl_video_cc_ahb_clk_src[] = {
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F(19200000, P_BI_TCXO, 1, 0, 0),
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{ }
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};
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static struct clk_rcg2 video_cc_ahb_clk_src = {
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.cmd_rcgr = 0x8060,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = video_cc_parent_map_0,
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.freq_tbl = ftbl_video_cc_ahb_clk_src,
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.hw_clk_ctrl = true,
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.clkr.hw.init = &(const struct clk_init_data) {
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.name = "video_cc_ahb_clk_src",
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.parent_data = video_cc_parent_data_0,
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.num_parents = ARRAY_SIZE(video_cc_parent_data_0),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_rcg2_shared_ops,
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},
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};
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static const struct freq_tbl ftbl_video_cc_mvs0_clk_src[] = {
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F(240000000, P_VIDEO_CC_PLL1_OUT_MAIN, 2, 0, 0),
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F(338000000, P_VIDEO_CC_PLL1_OUT_MAIN, 2, 0, 0),
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F(420000000, P_VIDEO_CC_PLL1_OUT_MAIN, 2, 0, 0),
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F(444000000, P_VIDEO_CC_PLL1_OUT_MAIN, 2, 0, 0),
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F(600000000, P_VIDEO_CC_PLL1_OUT_MAIN, 2, 0, 0),
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F(630000000, P_VIDEO_CC_PLL1_OUT_MAIN, 2, 0, 0),
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F(800000000, P_VIDEO_CC_PLL1_OUT_MAIN, 2, 0, 0),
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F(1000000000, P_VIDEO_CC_PLL1_OUT_MAIN, 2, 0, 0),
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{ }
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};
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static struct clk_rcg2 video_cc_mvs0_clk_src = {
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.cmd_rcgr = 0x8030,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = video_cc_parent_map_1,
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.freq_tbl = ftbl_video_cc_mvs0_clk_src,
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.hw_clk_ctrl = true,
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.clkr.hw.init = &(const struct clk_init_data) {
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.name = "video_cc_mvs0_clk_src",
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.parent_data = video_cc_parent_data_1,
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.num_parents = ARRAY_SIZE(video_cc_parent_data_1),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_rcg2_shared_ops,
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},
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};
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static const struct freq_tbl ftbl_video_cc_mvs0b_clk_src[] = {
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F(240000000, P_VIDEO_CC_PLL2_OUT_MAIN, 2, 0, 0),
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F(338000000, P_VIDEO_CC_PLL2_OUT_MAIN, 2, 0, 0),
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F(420000000, P_VIDEO_CC_PLL2_OUT_MAIN, 2, 0, 0),
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F(444000000, P_VIDEO_CC_PLL2_OUT_MAIN, 2, 0, 0),
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F(533000000, P_VIDEO_CC_PLL2_OUT_MAIN, 2, 0, 0),
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F(630000000, P_VIDEO_CC_PLL2_OUT_MAIN, 2, 0, 0),
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F(800000000, P_VIDEO_CC_PLL2_OUT_MAIN, 2, 0, 0),
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{ }
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};
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static struct clk_rcg2 video_cc_mvs0b_clk_src = {
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.cmd_rcgr = 0x8018,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = video_cc_parent_map_2,
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.freq_tbl = ftbl_video_cc_mvs0b_clk_src,
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.hw_clk_ctrl = true,
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.clkr.hw.init = &(const struct clk_init_data) {
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.name = "video_cc_mvs0b_clk_src",
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.parent_data = video_cc_parent_data_2,
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.num_parents = ARRAY_SIZE(video_cc_parent_data_2),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_rcg2_shared_ops,
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},
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};
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static const struct freq_tbl ftbl_video_cc_mvs0c_clk_src[] = {
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F(360000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
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F(507000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
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F(630000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
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F(666000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
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F(800000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
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F(1104000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
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F(1260000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
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{ }
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};
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static struct clk_rcg2 video_cc_mvs0c_clk_src = {
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.cmd_rcgr = 0x8048,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = video_cc_parent_map_3,
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.freq_tbl = ftbl_video_cc_mvs0c_clk_src,
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.hw_clk_ctrl = true,
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.clkr.hw.init = &(const struct clk_init_data) {
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.name = "video_cc_mvs0c_clk_src",
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.parent_data = video_cc_parent_data_3,
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.num_parents = ARRAY_SIZE(video_cc_parent_data_3),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_rcg2_shared_ops,
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},
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};
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static struct clk_rcg2 video_cc_xo_clk_src = {
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.cmd_rcgr = 0x8194,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = video_cc_parent_map_0,
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.freq_tbl = ftbl_video_cc_ahb_clk_src,
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.clkr.hw.init = &(const struct clk_init_data) {
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.name = "video_cc_xo_clk_src",
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.parent_data = video_cc_parent_data_0,
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.num_parents = ARRAY_SIZE(video_cc_parent_data_0),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_rcg2_ops,
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},
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};
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static struct clk_branch video_cc_mvs0_clk = {
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.halt_reg = 0x80d0,
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.halt_check = BRANCH_HALT_VOTED,
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.hwcg_reg = 0x80d0,
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.hwcg_bit = 1,
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.clkr = {
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.enable_reg = 0x80d0,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "video_cc_mvs0_clk",
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.parent_hws = (const struct clk_hw*[]) {
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&video_cc_mvs0_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_mem_branch video_cc_mvs0_freerun_clk = {
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.mem_enable_reg = 0x80e4,
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.mem_ack_reg = 0x80e4,
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.mem_enable_mask = BIT(3),
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.mem_enable_ack_mask = GENMASK(11, 10),
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.mem_enable_invert = true,
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.branch = {
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.halt_reg = 0x80e0,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x80e0,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "video_cc_mvs0_freerun_clk",
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.parent_hws = (const struct clk_hw*[]) {
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&video_cc_mvs0_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_mem_ops,
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},
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},
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},
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};
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static struct clk_branch video_cc_mvs0_shift_clk = {
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.halt_reg = 0x81b4,
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.halt_check = BRANCH_HALT_VOTED,
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.hwcg_reg = 0x81b4,
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.hwcg_bit = 1,
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.clkr = {
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.enable_reg = 0x81b4,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "video_cc_mvs0_shift_clk",
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.parent_hws = (const struct clk_hw*[]) {
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&video_cc_xo_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch video_cc_mvs0_vpp0_clk = {
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.halt_reg = 0x8134,
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.halt_check = BRANCH_HALT_VOTED,
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.hwcg_reg = 0x8134,
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.hwcg_bit = 1,
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.clkr = {
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.enable_reg = 0x8134,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "video_cc_mvs0_vpp0_clk",
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.parent_hws = (const struct clk_hw*[]) {
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&video_cc_mvs0_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch video_cc_mvs0_vpp0_freerun_clk = {
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.halt_reg = 0x8144,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x8144,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "video_cc_mvs0_vpp0_freerun_clk",
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.parent_hws = (const struct clk_hw*[]) {
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&video_cc_mvs0_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch video_cc_mvs0b_clk = {
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.halt_reg = 0x80bc,
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.halt_check = BRANCH_HALT_VOTED,
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.hwcg_reg = 0x80bc,
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.hwcg_bit = 1,
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.clkr = {
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.enable_reg = 0x80bc,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "video_cc_mvs0b_clk",
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.parent_hws = (const struct clk_hw*[]) {
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&video_cc_mvs0b_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch video_cc_mvs0b_freerun_clk = {
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.halt_reg = 0x80cc,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x80cc,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "video_cc_mvs0b_freerun_clk",
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.parent_hws = (const struct clk_hw*[]) {
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&video_cc_mvs0b_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch video_cc_mvs0c_clk = {
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.halt_reg = 0x8164,
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.halt_check = BRANCH_HALT_VOTED,
|
|
.hwcg_reg = 0x8164,
|
|
.hwcg_bit = 1,
|
|
.clkr = {
|
|
.enable_reg = 0x8164,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "video_cc_mvs0c_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&video_cc_mvs0c_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch video_cc_mvs0c_debug_clk = {
|
|
.halt_reg = 0x81c0,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x81c0,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "video_cc_mvs0c_debug_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&video_cc_mvs0c_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch video_cc_mvs0c_freerun_clk = {
|
|
.halt_reg = 0x8174,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x8174,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "video_cc_mvs0c_freerun_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&video_cc_mvs0c_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch video_cc_mvs0c_shift_clk = {
|
|
.halt_reg = 0x81b8,
|
|
.halt_check = BRANCH_HALT_VOTED,
|
|
.hwcg_reg = 0x81b8,
|
|
.hwcg_bit = 1,
|
|
.clkr = {
|
|
.enable_reg = 0x81b8,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "video_cc_mvs0c_shift_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&video_cc_xo_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct gdsc video_cc_mvs0c_gdsc = {
|
|
.gdscr = 0x814c,
|
|
.en_rest_wait_val = 0x2,
|
|
.en_few_wait_val = 0x2,
|
|
.clk_dis_wait_val = 0x6,
|
|
.pd = {
|
|
.name = "video_cc_mvs0c_gdsc",
|
|
},
|
|
.pwrsts = PWRSTS_OFF_ON,
|
|
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
|
|
};
|
|
|
|
static struct gdsc video_cc_mvs0_gdsc = {
|
|
.gdscr = 0x80a8,
|
|
.en_rest_wait_val = 0x2,
|
|
.en_few_wait_val = 0x2,
|
|
.clk_dis_wait_val = 0x6,
|
|
.pd = {
|
|
.name = "video_cc_mvs0_gdsc",
|
|
},
|
|
.parent = &video_cc_mvs0c_gdsc.pd,
|
|
.pwrsts = PWRSTS_OFF_ON,
|
|
.flags = HW_CTRL_TRIGGER | POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
|
|
};
|
|
|
|
static struct gdsc video_cc_mvs0_vpp0_gdsc = {
|
|
.gdscr = 0x8120,
|
|
.en_rest_wait_val = 0x2,
|
|
.en_few_wait_val = 0x2,
|
|
.clk_dis_wait_val = 0xf,
|
|
.pd = {
|
|
.name = "video_cc_mvs0_vpp0_gdsc",
|
|
},
|
|
.pwrsts = PWRSTS_OFF_ON,
|
|
.flags = HW_CTRL_TRIGGER | POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
|
|
};
|
|
|
|
static struct clk_regmap *video_cc_maili_clocks[] = {
|
|
[VIDEO_CC_AHB_CLK_SRC] = &video_cc_ahb_clk_src.clkr,
|
|
[VIDEO_CC_MVS0_CLK] = &video_cc_mvs0_clk.clkr,
|
|
[VIDEO_CC_MVS0_CLK_SRC] = &video_cc_mvs0_clk_src.clkr,
|
|
[VIDEO_CC_MVS0_FREERUN_CLK] = &video_cc_mvs0_freerun_clk.branch.clkr,
|
|
[VIDEO_CC_MVS0_SHIFT_CLK] = &video_cc_mvs0_shift_clk.clkr,
|
|
[VIDEO_CC_MVS0_VPP0_CLK] = &video_cc_mvs0_vpp0_clk.clkr,
|
|
[VIDEO_CC_MVS0_VPP0_FREERUN_CLK] = &video_cc_mvs0_vpp0_freerun_clk.clkr,
|
|
[VIDEO_CC_MVS0B_CLK] = &video_cc_mvs0b_clk.clkr,
|
|
[VIDEO_CC_MVS0B_CLK_SRC] = &video_cc_mvs0b_clk_src.clkr,
|
|
[VIDEO_CC_MVS0B_FREERUN_CLK] = &video_cc_mvs0b_freerun_clk.clkr,
|
|
[VIDEO_CC_MVS0C_CLK] = &video_cc_mvs0c_clk.clkr,
|
|
[VIDEO_CC_MVS0C_CLK_SRC] = &video_cc_mvs0c_clk_src.clkr,
|
|
[VIDEO_CC_MVS0C_DEBUG_CLK] = &video_cc_mvs0c_debug_clk.clkr,
|
|
[VIDEO_CC_MVS0C_FREERUN_CLK] = &video_cc_mvs0c_freerun_clk.clkr,
|
|
[VIDEO_CC_MVS0C_SHIFT_CLK] = &video_cc_mvs0c_shift_clk.clkr,
|
|
[VIDEO_CC_PLL0] = &video_cc_pll0.clkr,
|
|
[VIDEO_CC_PLL1] = &video_cc_pll1.clkr,
|
|
[VIDEO_CC_PLL2] = &video_cc_pll2.clkr,
|
|
[VIDEO_CC_XO_CLK_SRC] = &video_cc_xo_clk_src.clkr,
|
|
};
|
|
|
|
static struct gdsc *video_cc_maili_gdscs[] = {
|
|
[VIDEO_CC_MVS0_GDSC] = &video_cc_mvs0_gdsc,
|
|
[VIDEO_CC_MVS0_VPP0_GDSC] = &video_cc_mvs0_vpp0_gdsc,
|
|
[VIDEO_CC_MVS0C_GDSC] = &video_cc_mvs0c_gdsc,
|
|
};
|
|
|
|
static const struct qcom_reset_map video_cc_maili_resets[] = {
|
|
[VIDEO_CC_INTERFACE_BCR] = { 0x8178 },
|
|
[VIDEO_CC_MVS0_BCR] = { 0x80a4 },
|
|
[VIDEO_CC_MVS0_CLK_ARES] = { 0x80d0, 2 },
|
|
[VIDEO_CC_MVS0_FREERUN_CLK_ARES] = { 0x80e0, 2 },
|
|
[VIDEO_CC_MVS0_VPP0_BCR] = { 0x811c },
|
|
[VIDEO_CC_MVS0C_BCR] = { 0x8148 },
|
|
[VIDEO_CC_MVS0C_CLK_ARES] = { 0x8164, 2 },
|
|
[VIDEO_CC_MVS0C_FREERUN_CLK_ARES] = { 0x8174, 2 },
|
|
[VIDEO_CC_XO_CLK_ARES] = { 0x81ac, 2 },
|
|
};
|
|
|
|
static struct clk_alpha_pll *video_cc_maili_plls[] = {
|
|
&video_cc_pll0,
|
|
&video_cc_pll1,
|
|
&video_cc_pll2,
|
|
};
|
|
|
|
static const u32 video_cc_maili_critical_cbcrs[] = {
|
|
0x817c, /* VIDEO_CC_AHB_CLK */
|
|
0x81bc, /* VIDEO_CC_SLEEP_CLK */
|
|
0x81b0, /* VIDEO_CC_TS_XO_CLK */
|
|
0x81ac, /* VIDEO_CC_XO_CLK */
|
|
};
|
|
|
|
static const struct regmap_config video_cc_maili_regmap_config = {
|
|
.reg_bits = 32,
|
|
.reg_stride = 4,
|
|
.val_bits = 32,
|
|
.max_register = 0xa010,
|
|
.fast_io = true,
|
|
};
|
|
|
|
static void clk_maili_regs_configure(struct device *dev, struct regmap *regmap)
|
|
{
|
|
/*
|
|
* Enable clk_on sync for MVS0 and VPP clocks as per the
|
|
* hardware recommendation.
|
|
*/
|
|
regmap_set_bits(regmap, 0x9f24, BIT(0));
|
|
|
|
/*
|
|
* Update ACCU configuration for MVS0 CFG3, MVS0 VPP0 CFG3,
|
|
* MVS0C CFG3 GDSCRs as per the hardware recommendation.
|
|
*/
|
|
regmap_set_bits(regmap, 0x80b4, ACCU_CFG_MASK);
|
|
regmap_set_bits(regmap, 0x812c, ACCU_CFG_MASK);
|
|
regmap_set_bits(regmap, 0x8158, ACCU_CFG_MASK);
|
|
}
|
|
|
|
static const struct qcom_cc_driver_data video_cc_maili_driver_data = {
|
|
.alpha_plls = video_cc_maili_plls,
|
|
.num_alpha_plls = ARRAY_SIZE(video_cc_maili_plls),
|
|
.clk_cbcrs = video_cc_maili_critical_cbcrs,
|
|
.num_clk_cbcrs = ARRAY_SIZE(video_cc_maili_critical_cbcrs),
|
|
.clk_regs_configure = clk_maili_regs_configure,
|
|
};
|
|
|
|
static const struct qcom_cc_desc video_cc_maili_desc = {
|
|
.config = &video_cc_maili_regmap_config,
|
|
.clks = video_cc_maili_clocks,
|
|
.num_clks = ARRAY_SIZE(video_cc_maili_clocks),
|
|
.resets = video_cc_maili_resets,
|
|
.num_resets = ARRAY_SIZE(video_cc_maili_resets),
|
|
.gdscs = video_cc_maili_gdscs,
|
|
.num_gdscs = ARRAY_SIZE(video_cc_maili_gdscs),
|
|
.use_rpm = true,
|
|
.driver_data = &video_cc_maili_driver_data,
|
|
};
|
|
|
|
static const struct of_device_id video_cc_maili_match_table[] = {
|
|
{ .compatible = "qcom,maili-videocc" },
|
|
{ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, video_cc_maili_match_table);
|
|
|
|
static int video_cc_maili_probe(struct platform_device *pdev)
|
|
{
|
|
return qcom_cc_probe(pdev, &video_cc_maili_desc);
|
|
}
|
|
|
|
static struct platform_driver video_cc_maili_driver = {
|
|
.probe = video_cc_maili_probe,
|
|
.driver = {
|
|
.name = "videocc-maili",
|
|
.of_match_table = video_cc_maili_match_table,
|
|
},
|
|
};
|
|
|
|
module_platform_driver(video_cc_maili_driver);
|
|
|
|
MODULE_DESCRIPTION("QTI VIDEOCC Maili Driver");
|
|
MODULE_LICENSE("GPL");
|