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47f2e6e1ce
Add support for the GPU clock controllers (GPUCC) on the Qualcomm Nord platform. The platform includes two GPU clock controller instances,GPUCC and GPU2CC. Register support for both controllers, which provide clocks required for the graphics subsystem. Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Reviewed-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260724-nords_mm_v1-v3-6-32b45232217f@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
546 lines
14 KiB
C
546 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
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*/
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <dt-bindings/clock/qcom,nord-gpu2cc.h>
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#include "clk-alpha-pll.h"
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#include "clk-branch.h"
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#include "clk-pll.h"
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#include "clk-rcg.h"
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#include "clk-regmap.h"
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#include "clk-regmap-divider.h"
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#include "clk-regmap-mux.h"
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#include "common.h"
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#include "gdsc.h"
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#include "reset.h"
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enum {
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DT_BI_TCXO,
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DT_GPLL0_OUT_MAIN,
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DT_GPLL0_OUT_MAIN_DIV,
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};
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enum {
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P_BI_TCXO,
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P_GPLL0_OUT_MAIN,
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P_GPLL0_OUT_MAIN_DIV,
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P_GPU_2_CC_PLL0_OUT_MAIN,
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P_GPU_2_CC_PLL1_OUT_MAIN,
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};
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static const struct pll_vco lucid_ole_vco[] = {
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{ 249600000, 2300000000, 0 },
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};
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/* 934.0 MHz Configuration */
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static const struct alpha_pll_config gpu_2_cc_pll0_config = {
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.l = 0x30,
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.alpha = 0xa555,
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.config_ctl_val = 0x20485699,
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.config_ctl_hi_val = 0x00182261,
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.config_ctl_hi1_val = 0x82aa299c,
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.test_ctl_val = 0x00000000,
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.test_ctl_hi_val = 0x00000003,
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.test_ctl_hi1_val = 0x00009000,
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.test_ctl_hi2_val = 0x00000034,
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.user_ctl_val = 0x00000000,
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.user_ctl_hi_val = 0x00400005,
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};
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static struct clk_alpha_pll gpu_2_cc_pll0 = {
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.offset = 0x0,
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.config = &gpu_2_cc_pll0_config,
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.vco_table = lucid_ole_vco,
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.num_vco = ARRAY_SIZE(lucid_ole_vco),
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
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.clkr = {
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.hw.init = &(const struct clk_init_data) {
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.name = "gpu_2_cc_pll0",
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.parent_data = &(const struct clk_parent_data) {
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.index = DT_BI_TCXO,
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},
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.num_parents = 1,
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.ops = &clk_alpha_pll_lucid_evo_ops,
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},
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},
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};
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/* 1100.0 MHz Configuration */
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static const struct alpha_pll_config gpu_2_cc_pll1_config = {
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.l = 0x39,
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.alpha = 0x4aaa,
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.config_ctl_val = 0x20485699,
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.config_ctl_hi_val = 0x00182261,
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.config_ctl_hi1_val = 0x82aa299c,
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.test_ctl_val = 0x00000000,
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.test_ctl_hi_val = 0x00000003,
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.test_ctl_hi1_val = 0x00009000,
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.test_ctl_hi2_val = 0x00000034,
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.user_ctl_val = 0x00000000,
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.user_ctl_hi_val = 0x00400005,
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};
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static struct clk_alpha_pll gpu_2_cc_pll1 = {
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.offset = 0x1000,
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.config = &gpu_2_cc_pll1_config,
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.vco_table = lucid_ole_vco,
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.num_vco = ARRAY_SIZE(lucid_ole_vco),
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
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.clkr = {
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.hw.init = &(const struct clk_init_data) {
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.name = "gpu_2_cc_pll1",
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.parent_data = &(const struct clk_parent_data) {
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.index = DT_BI_TCXO,
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},
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.num_parents = 1,
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.ops = &clk_alpha_pll_lucid_evo_ops,
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},
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},
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};
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static const struct parent_map gpu_2_cc_parent_map_0[] = {
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{ P_BI_TCXO, 0 },
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{ P_GPLL0_OUT_MAIN, 5 },
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{ P_GPLL0_OUT_MAIN_DIV, 6 },
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};
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static const struct clk_parent_data gpu_2_cc_parent_data_0[] = {
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{ .index = DT_BI_TCXO },
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{ .index = DT_GPLL0_OUT_MAIN },
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{ .index = DT_GPLL0_OUT_MAIN_DIV },
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};
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static const struct parent_map gpu_2_cc_parent_map_1[] = {
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{ P_BI_TCXO, 0 },
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{ P_GPU_2_CC_PLL0_OUT_MAIN, 1 },
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{ P_GPU_2_CC_PLL1_OUT_MAIN, 3 },
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{ P_GPLL0_OUT_MAIN, 5 },
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{ P_GPLL0_OUT_MAIN_DIV, 6 },
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};
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static const struct clk_parent_data gpu_2_cc_parent_data_1[] = {
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{ .index = DT_BI_TCXO },
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{ .hw = &gpu_2_cc_pll0.clkr.hw },
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{ .hw = &gpu_2_cc_pll1.clkr.hw },
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{ .index = DT_GPLL0_OUT_MAIN },
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{ .index = DT_GPLL0_OUT_MAIN_DIV },
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};
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static const struct parent_map gpu_2_cc_parent_map_2[] = {
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{ P_BI_TCXO, 0 },
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{ P_GPU_2_CC_PLL1_OUT_MAIN, 3 },
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{ P_GPLL0_OUT_MAIN, 5 },
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{ P_GPLL0_OUT_MAIN_DIV, 6 },
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};
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static const struct clk_parent_data gpu_2_cc_parent_data_2[] = {
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{ .index = DT_BI_TCXO },
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{ .hw = &gpu_2_cc_pll1.clkr.hw },
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{ .index = DT_GPLL0_OUT_MAIN },
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{ .index = DT_GPLL0_OUT_MAIN_DIV },
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};
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static const struct freq_tbl ftbl_gpu_2_cc_ff_clk_src[] = {
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F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
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{ }
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};
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static struct clk_rcg2 gpu_2_cc_ff_clk_src = {
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.cmd_rcgr = 0x91c4,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = gpu_2_cc_parent_map_0,
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.freq_tbl = ftbl_gpu_2_cc_ff_clk_src,
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.hw_clk_ctrl = true,
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.clkr.hw.init = &(const struct clk_init_data) {
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.name = "gpu_2_cc_ff_clk_src",
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.parent_data = gpu_2_cc_parent_data_0,
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.num_parents = ARRAY_SIZE(gpu_2_cc_parent_data_0),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_rcg2_shared_ops,
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},
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};
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static const struct freq_tbl ftbl_gpu_2_cc_gmu_clk_src[] = {
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F(550000000, P_GPU_2_CC_PLL1_OUT_MAIN, 2, 0, 0),
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{ }
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};
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static struct clk_rcg2 gpu_2_cc_gmu_clk_src = {
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.cmd_rcgr = 0x9174,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = gpu_2_cc_parent_map_1,
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.freq_tbl = ftbl_gpu_2_cc_gmu_clk_src,
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.hw_clk_ctrl = true,
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.clkr.hw.init = &(const struct clk_init_data) {
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.name = "gpu_2_cc_gmu_clk_src",
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.parent_data = gpu_2_cc_parent_data_1,
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.num_parents = ARRAY_SIZE(gpu_2_cc_parent_data_1),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_rcg2_shared_ops,
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},
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};
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static struct clk_rcg2 gpu_2_cc_hub_clk_src = {
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.cmd_rcgr = 0x91a8,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = gpu_2_cc_parent_map_2,
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.freq_tbl = ftbl_gpu_2_cc_ff_clk_src,
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.hw_clk_ctrl = true,
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.clkr.hw.init = &(const struct clk_init_data) {
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.name = "gpu_2_cc_hub_clk_src",
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.parent_data = gpu_2_cc_parent_data_2,
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.num_parents = ARRAY_SIZE(gpu_2_cc_parent_data_2),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_rcg2_shared_ops,
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},
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};
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static struct clk_branch gpu_2_cc_ahb_clk = {
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.halt_reg = 0x90cc,
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.halt_check = BRANCH_HALT_VOTED,
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.clkr = {
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.enable_reg = 0x90cc,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "gpu_2_cc_ahb_clk",
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.parent_hws = (const struct clk_hw*[]) {
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&gpu_2_cc_hub_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpu_2_cc_crc_ahb_clk = {
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.halt_reg = 0x90d0,
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.halt_check = BRANCH_HALT_VOTED,
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.clkr = {
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.enable_reg = 0x90d0,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "gpu_2_cc_crc_ahb_clk",
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.parent_hws = (const struct clk_hw*[]) {
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&gpu_2_cc_hub_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpu_2_cc_cx_accu_shift_clk = {
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.halt_reg = 0x9114,
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.halt_check = BRANCH_HALT_VOTED,
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.clkr = {
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.enable_reg = 0x9114,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "gpu_2_cc_cx_accu_shift_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpu_2_cc_cx_ff_clk = {
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.halt_reg = 0x9100,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x9100,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "gpu_2_cc_cx_ff_clk",
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.parent_hws = (const struct clk_hw*[]) {
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&gpu_2_cc_ff_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpu_2_cc_cx_gmu_clk = {
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.halt_reg = 0x90e8,
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.halt_check = BRANCH_HALT_VOTED,
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.clkr = {
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.enable_reg = 0x90e8,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "gpu_2_cc_cx_gmu_clk",
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.parent_hws = (const struct clk_hw*[]) {
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&gpu_2_cc_gmu_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_aon_ops,
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},
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},
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};
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static struct clk_branch gpu_2_cc_cxo_clk = {
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.halt_reg = 0x90f8,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x90f8,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "gpu_2_cc_cxo_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpu_2_cc_freq_measure_clk = {
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.halt_reg = 0x9008,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x9008,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "gpu_2_cc_freq_measure_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpu_2_cc_gpu_smmu_vote_clk = {
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.halt_reg = 0x7000,
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.halt_check = BRANCH_HALT_VOTED,
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.clkr = {
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.enable_reg = 0x7000,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "gpu_2_cc_gpu_smmu_vote_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpu_2_cc_hub_aon_clk = {
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.halt_reg = 0x91a4,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x91a4,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "gpu_2_cc_hub_aon_clk",
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.parent_hws = (const struct clk_hw*[]) {
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&gpu_2_cc_hub_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_aon_ops,
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},
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},
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};
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static struct clk_branch gpu_2_cc_hub_cx_int_clk = {
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.halt_reg = 0x90fc,
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.halt_check = BRANCH_HALT_VOTED,
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.clkr = {
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.enable_reg = 0x90fc,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "gpu_2_cc_hub_cx_int_clk",
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.parent_hws = (const struct clk_hw*[]) {
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&gpu_2_cc_hub_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_aon_ops,
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},
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},
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};
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static struct clk_branch gpu_2_cc_memnoc_gfx_clk = {
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.halt_reg = 0x9104,
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.halt_check = BRANCH_HALT_VOTED,
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.clkr = {
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.enable_reg = 0x9104,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "gpu_2_cc_memnoc_gfx_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpu_2_cc_mnd1x_0_gfx3d_clk = {
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.halt_reg = 0x9164,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x9164,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "gpu_2_cc_mnd1x_0_gfx3d_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpu_2_cc_mnd1x_1_gfx3d_clk = {
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.halt_reg = 0x9168,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x9168,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "gpu_2_cc_mnd1x_1_gfx3d_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpu_2_cc_sleep_clk = {
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.halt_reg = 0x90e0,
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.halt_check = BRANCH_HALT_SKIP,
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.clkr = {
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.enable_reg = 0x90e0,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "gpu_2_cc_sleep_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct gdsc gpu_2_cc_cx_gdsc = {
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.gdscr = 0x9090,
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.gds_hw_ctrl = 0x90a4,
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.en_rest_wait_val = 0x2,
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.en_few_wait_val = 0x2,
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.clk_dis_wait_val = 0xf,
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.pd = {
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.name = "gpu_2_cc_cx_gdsc",
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},
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.pwrsts = PWRSTS_OFF_ON,
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.flags = VOTABLE | RETAIN_FF_ENABLE,
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};
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static struct gdsc gpu_2_cc_gx_gdsc = {
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.gdscr = 0x9034,
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.clamp_io_ctrl = 0x9504,
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.en_rest_wait_val = 0x2,
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.en_few_wait_val = 0x2,
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.clk_dis_wait_val = 0xf,
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.pd = {
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.name = "gpu_2_cc_gx_gdsc",
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.power_on = gdsc_gx_do_nothing_enable,
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},
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.pwrsts = PWRSTS_OFF_ON,
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.flags = CLAMP_IO | POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
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};
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|
|
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static struct clk_regmap *gpu_2_cc_nord_clocks[] = {
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[GPU_2_CC_AHB_CLK] = &gpu_2_cc_ahb_clk.clkr,
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|
[GPU_2_CC_CRC_AHB_CLK] = &gpu_2_cc_crc_ahb_clk.clkr,
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|
[GPU_2_CC_CX_ACCU_SHIFT_CLK] = &gpu_2_cc_cx_accu_shift_clk.clkr,
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|
[GPU_2_CC_CX_FF_CLK] = &gpu_2_cc_cx_ff_clk.clkr,
|
|
[GPU_2_CC_CX_GMU_CLK] = &gpu_2_cc_cx_gmu_clk.clkr,
|
|
[GPU_2_CC_CXO_CLK] = &gpu_2_cc_cxo_clk.clkr,
|
|
[GPU_2_CC_FF_CLK_SRC] = &gpu_2_cc_ff_clk_src.clkr,
|
|
[GPU_2_CC_FREQ_MEASURE_CLK] = &gpu_2_cc_freq_measure_clk.clkr,
|
|
[GPU_2_CC_GMU_CLK_SRC] = &gpu_2_cc_gmu_clk_src.clkr,
|
|
[GPU_2_CC_GPU_SMMU_VOTE_CLK] = &gpu_2_cc_gpu_smmu_vote_clk.clkr,
|
|
[GPU_2_CC_HUB_AON_CLK] = &gpu_2_cc_hub_aon_clk.clkr,
|
|
[GPU_2_CC_HUB_CLK_SRC] = &gpu_2_cc_hub_clk_src.clkr,
|
|
[GPU_2_CC_HUB_CX_INT_CLK] = &gpu_2_cc_hub_cx_int_clk.clkr,
|
|
[GPU_2_CC_MEMNOC_GFX_CLK] = &gpu_2_cc_memnoc_gfx_clk.clkr,
|
|
[GPU_2_CC_MND1X_0_GFX3D_CLK] = &gpu_2_cc_mnd1x_0_gfx3d_clk.clkr,
|
|
[GPU_2_CC_MND1X_1_GFX3D_CLK] = &gpu_2_cc_mnd1x_1_gfx3d_clk.clkr,
|
|
[GPU_2_CC_PLL0] = &gpu_2_cc_pll0.clkr,
|
|
[GPU_2_CC_PLL1] = &gpu_2_cc_pll1.clkr,
|
|
[GPU_2_CC_SLEEP_CLK] = &gpu_2_cc_sleep_clk.clkr,
|
|
};
|
|
|
|
static struct gdsc *gpu_2_cc_nord_gdscs[] = {
|
|
[GPU_2_CC_CX_GDSC] = &gpu_2_cc_cx_gdsc,
|
|
[GPU_2_CC_GX_GDSC] = &gpu_2_cc_gx_gdsc,
|
|
};
|
|
|
|
static const struct qcom_reset_map gpu_2_cc_nord_resets[] = {
|
|
[GPU_2_CC_ACD_BCR] = { 0x918c },
|
|
[GPU_2_CC_CB_BCR] = { 0x9198 },
|
|
[GPU_2_CC_CX_BCR] = { 0x908c },
|
|
[GPU_2_CC_FAST_HUB_BCR] = { 0x91a0 },
|
|
[GPU_2_CC_FF_BCR] = { 0x91c0 },
|
|
[GPU_2_CC_GFX3D_AON_BCR] = { 0x9118 },
|
|
[GPU_2_CC_GMU_BCR] = { 0x9170 },
|
|
[GPU_2_CC_GX_BCR] = { 0x9030 },
|
|
[GPU_2_CC_XO_BCR] = { 0x9000 },
|
|
};
|
|
|
|
static struct clk_alpha_pll *gpu_2_cc_nord_plls[] = {
|
|
&gpu_2_cc_pll0,
|
|
&gpu_2_cc_pll1,
|
|
};
|
|
|
|
static const u32 gpu_2_cc_nord_critical_cbcrs[] = {
|
|
0x9004, /* GPU_2_CC_CXO_AON_CLK */
|
|
0x900c, /* GPU_2_CC_DEMET_CLK */
|
|
};
|
|
|
|
static const struct regmap_config gpu_2_cc_nord_regmap_config = {
|
|
.reg_bits = 32,
|
|
.reg_stride = 4,
|
|
.val_bits = 32,
|
|
.max_register = 0x9ff0,
|
|
.fast_io = true,
|
|
};
|
|
|
|
static const struct qcom_cc_driver_data gpu_2_cc_nord_driver_data = {
|
|
.alpha_plls = gpu_2_cc_nord_plls,
|
|
.num_alpha_plls = ARRAY_SIZE(gpu_2_cc_nord_plls),
|
|
.clk_cbcrs = gpu_2_cc_nord_critical_cbcrs,
|
|
.num_clk_cbcrs = ARRAY_SIZE(gpu_2_cc_nord_critical_cbcrs),
|
|
};
|
|
|
|
static const struct qcom_cc_desc gpu_2_cc_nord_desc = {
|
|
.config = &gpu_2_cc_nord_regmap_config,
|
|
.clks = gpu_2_cc_nord_clocks,
|
|
.num_clks = ARRAY_SIZE(gpu_2_cc_nord_clocks),
|
|
.resets = gpu_2_cc_nord_resets,
|
|
.num_resets = ARRAY_SIZE(gpu_2_cc_nord_resets),
|
|
.gdscs = gpu_2_cc_nord_gdscs,
|
|
.num_gdscs = ARRAY_SIZE(gpu_2_cc_nord_gdscs),
|
|
.use_rpm = true,
|
|
.driver_data = &gpu_2_cc_nord_driver_data,
|
|
};
|
|
|
|
static const struct of_device_id gpu_2_cc_nord_match_table[] = {
|
|
{ .compatible = "qcom,nord-gpu2cc" },
|
|
{ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, gpu_2_cc_nord_match_table);
|
|
|
|
static int gpu_2_cc_nord_probe(struct platform_device *pdev)
|
|
{
|
|
return qcom_cc_probe(pdev, &gpu_2_cc_nord_desc);
|
|
}
|
|
|
|
static struct platform_driver gpu_2_cc_nord_driver = {
|
|
.probe = gpu_2_cc_nord_probe,
|
|
.driver = {
|
|
.name = "gpu2cc-nord",
|
|
.of_match_table = gpu_2_cc_nord_match_table,
|
|
},
|
|
};
|
|
|
|
module_platform_driver(gpu_2_cc_nord_driver);
|
|
|
|
MODULE_DESCRIPTION("QTI GPU2CC Nord Driver");
|
|
MODULE_LICENSE("GPL");
|