Joey Lu e1311954cb clk: nuvoton: ma35d1: fix ma35d1_clk_pll_determine_rate logic ... ma35d1_clk_pll_determine_rate() called ma35d1_pll_find_closest() unconditionally before the switch statement, and then every case branch overwrote pll_freq by reading the current hardware registers. For CAPLL and DDRPLL this means find_closest() ran unnecessarily (and incorrectly, since those PLLs are read-only) and its result was silently discarded. Fix by moving the find_closest() call inside the APLL/EPLL/VPLL branch where it belongs. Group CAPLL and DDRPLL together as read-only PLLs that simply report their current rate; handle them with an explicit if/else to keep the CAPLL (SMIC design) and DDRPLL (standard design) paths distinct. Fixes: 691521a367 ("clk: nuvoton: Add clock driver for ma35d1 clock controller") Signed-off-by: Joey Lu <a0987203069@gmail.com> Signed-off-by: Brian Masney <bmasney@redhat.com>		2026-06-29 13:27:28 -04:00
..
clk-ma35d1-divider.c	clk: nuvoton: ma35d1-divider: convert from divider_round_rate() to divider_determine_rate()	2026-01-22 10:48:25 -05:00
clk-ma35d1-pll.c	clk: nuvoton: ma35d1: fix ma35d1_clk_pll_determine_rate logic	2026-06-29 13:27:28 -04:00
clk-ma35d1.c	clk: nuvoton: Convert to devm_platform_ioremap_resource()	2023-08-22 14:52:11 -07:00
clk-ma35d1.h
Kconfig	clk: nuvoton: Do not enable by default during compile testing	2025-06-20 00:21:15 -07:00
Makefile