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8d92085fd7
Add driver for the ESWIN EIC7700 high-speed peripherals system clock controller and register an auxiliary device for system reset controller which is named as "hsp-reset". Reviewed-by: Brian Masney <bmasney@redhat.com> Signed-off-by: Xuyang Dong <dongxuyang@eswincomputing.com> Signed-off-by: Brian Masney <bmasney@redhat.com>
346 lines
10 KiB
C
346 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright 2026, Beijing ESWIN Computing Technology Co., Ltd..
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* All rights reserved.
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*
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* ESWIN EIC7700 HSP Clock Driver
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*
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* Authors: Xuyang Dong <dongxuyang@eswincomputing.com>
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*/
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#include <linux/auxiliary_bus.h>
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#include <linux/clk-provider.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <dt-bindings/clock/eswin,eic7700-hspcrg.h>
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#include "common.h"
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#define EIC7700_HSP_SATA_REG 0x300
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#define EIC7700_HSP_MSHC0_REG 0x510
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#define EIC7700_HSP_MSHC1_REG 0x610
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#define EIC7700_HSP_MSHC2_REG 0x710
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#define EIC7700_HSP_USB0_REG 0x800
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#define EIC7700_HSP_USB0_REF_REG 0x83c
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#define EIC7700_HSP_USB1_REG 0x900
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#define EIC7700_HSP_USB1_REF_REG 0x93c
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#define USB_REF_XTAL24M 0x2a
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#define EIC7700_HSP_NR_CLKS (EIC7700_HSP_CLK_GATE_SATA + 1)
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struct eic7700_hsp_clk_gate {
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struct clk_hw hw;
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unsigned int id;
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struct regmap *regmap;
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unsigned int reg;
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unsigned int ref_reg;
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const char *name;
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const struct clk_parent_data *parent_data;
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unsigned long flags;
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unsigned int offset;
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unsigned int ref_offset;
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u8 bit_idx;
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};
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static const struct regmap_config eic7700_hsp_regmap_config = {
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.reg_bits = 32,
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.val_bits = 32,
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.max_register = 0x1ffc,
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.reg_stride = 4,
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.fast_io = true,
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.use_raw_spinlock = true,
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};
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static inline struct eic7700_hsp_clk_gate *to_gate_clk(struct clk_hw *hw)
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{
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return container_of(hw, struct eic7700_hsp_clk_gate, hw);
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}
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#define EIC7700_HSP_GATE(_id, _name, _pdata, _flags, _offset, _idx, \
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_ref_offset) \
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{ \
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.id = _id, \
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.name = _name, \
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.parent_data = _pdata, \
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.flags = _flags, \
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.offset = _offset, \
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.ref_offset = _ref_offset, \
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.bit_idx = _idx, \
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}
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static void hsp_clk_gate_endisable(struct clk_hw *hw, bool enable)
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{
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struct eic7700_hsp_clk_gate *gate = to_gate_clk(hw);
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if (enable) {
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/*
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* Hardware bug: The USB reference clock must be 24MHz.
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* The default register value after reset is invalid.
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* Workaround: Rewrite the correct value before enabling
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* the USB gate clock.
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*/
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regmap_update_bits(gate->regmap, gate->ref_reg, 0x3f,
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USB_REF_XTAL24M);
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}
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regmap_assign_bits(gate->regmap, gate->reg, BIT(gate->bit_idx), enable);
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}
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static int hsp_clk_gate_enable(struct clk_hw *hw)
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{
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hsp_clk_gate_endisable(hw, true);
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return 0;
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}
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static void hsp_clk_gate_disable(struct clk_hw *hw)
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{
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hsp_clk_gate_endisable(hw, false);
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}
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static int hsp_clk_gate_is_enabled(struct clk_hw *hw)
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{
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struct eic7700_hsp_clk_gate *gate = to_gate_clk(hw);
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unsigned int val;
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int ret;
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ret = regmap_read(gate->regmap, gate->reg, &val);
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if (ret != 0)
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return ret;
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return !!(val & BIT(gate->bit_idx));
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}
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static const struct clk_ops hsp_clk_gate_ops = {
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.enable = hsp_clk_gate_enable,
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.disable = hsp_clk_gate_disable,
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.is_enabled = hsp_clk_gate_is_enabled,
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};
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static struct clk_hw *
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hsp_clk_register_gate(struct device *dev, unsigned int id, const char *name,
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const struct clk_parent_data *parent_data,
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unsigned long flags, struct regmap *regmap,
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unsigned int reg, unsigned int ref_reg, u8 bit_idx)
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{
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struct eic7700_hsp_clk_gate *gate;
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struct clk_init_data init = {};
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struct clk_hw *hw;
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int ret;
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gate = devm_kzalloc(dev, sizeof(*gate), GFP_KERNEL);
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if (!gate)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.ops = &hsp_clk_gate_ops;
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init.flags = flags;
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init.parent_data = parent_data;
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init.num_parents = 1;
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gate->id = id;
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gate->regmap = regmap;
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gate->reg = reg;
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gate->ref_reg = ref_reg;
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gate->bit_idx = bit_idx;
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gate->hw.init = &init;
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hw = &gate->hw;
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ret = devm_clk_hw_register(dev, hw);
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if (ret)
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hw = ERR_PTR(ret);
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return hw;
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}
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static const struct clk_parent_data hsp_cfg[] = {
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{ .index = 0 }
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};
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static const struct clk_parent_data hsp_mmc[] = {
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{ .index = 1 }
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};
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static const struct clk_parent_data hsp_usb_sata[] = {
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{ .index = 2 }
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};
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static struct eswin_fixed_factor_clock eic7700_hsp_factor_clks[] = {
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ESWIN_FACTOR(EIC7700_HSP_CLK_FAC_CFG_DIV2, "factor_hsp_cfg_div2",
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hsp_cfg, 1, 2, 0),
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ESWIN_FACTOR(EIC7700_HSP_CLK_FAC_CFG_DIV4, "factor_hsp_cfg_div4",
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hsp_cfg, 1, 4, 0),
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ESWIN_FACTOR(EIC7700_HSP_CLK_FAC_MMC_DIV10, "factor_hsp_mmc_div10",
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hsp_mmc, 1, 10, 0),
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};
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static struct eswin_gate_clock eic7700_hsp_gate_clks[] = {
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ESWIN_GATE(EIC7700_HSP_CLK_GATE_SATA, "gate_clk_hsp_sata", hsp_usb_sata,
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CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
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EIC7700_HSP_SATA_REG, 28, 0),
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ESWIN_GATE(EIC7700_HSP_CLK_GATE_MSHC0_TMR, "gate_clk_hsp_mshc0_tmr",
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hsp_mmc, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
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EIC7700_HSP_MSHC0_REG, 8, 0),
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ESWIN_GATE(EIC7700_HSP_CLK_GATE_MSHC1_TMR, "gate_clk_hsp_mshc1_tmr",
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hsp_mmc, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
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EIC7700_HSP_MSHC1_REG, 8, 0),
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ESWIN_GATE(EIC7700_HSP_CLK_GATE_MSHC2_TMR, "gate_clk_hsp_mshc2_tmr",
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hsp_mmc, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
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EIC7700_HSP_MSHC2_REG, 8, 0),
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};
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static struct eic7700_hsp_clk_gate eic7700_hsp_spec_gate_clks[] = {
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EIC7700_HSP_GATE(EIC7700_HSP_CLK_GATE_USB0, "gate_clk_hsp_usb0",
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hsp_usb_sata, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
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EIC7700_HSP_USB0_REG, 28, EIC7700_HSP_USB0_REF_REG),
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EIC7700_HSP_GATE(EIC7700_HSP_CLK_GATE_USB1, "gate_clk_hsp_usb1",
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hsp_usb_sata, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
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EIC7700_HSP_USB1_REG, 28, EIC7700_HSP_USB1_REF_REG),
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};
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static const struct clk_parent_data mux_mmc_3mux1_p[] = {
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{ .fw_name = "cfg" },
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{ .hw = &eic7700_hsp_factor_clks[0].hw },
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{ .hw = &eic7700_hsp_factor_clks[1].hw },
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};
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static const struct clk_parent_data mux_mmc_2mux1_p[] = {
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{ .fw_name = "mmc" },
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{ .hw = &eic7700_hsp_factor_clks[2].hw },
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};
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static u32 mux_mmc_3mux1_tbl[] = { 0x0, 0x1, 0x3 };
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static struct eswin_mux_clock eic7700_hsp_mux_clks[] = {
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ESWIN_MUX_TBL(EIC7700_HSP_CLK_MUX_EMMC_3MUX1, "mux_hsp_emmc_3mux1",
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mux_mmc_3mux1_p, ARRAY_SIZE(mux_mmc_3mux1_p),
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CLK_SET_RATE_PARENT, EIC7700_HSP_MSHC0_REG, 16, 2, 0,
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mux_mmc_3mux1_tbl),
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ESWIN_MUX_TBL(EIC7700_HSP_CLK_MUX_SD0_3MUX1, "mux_hsp_sd0_3mux1",
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mux_mmc_3mux1_p, ARRAY_SIZE(mux_mmc_3mux1_p),
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CLK_SET_RATE_PARENT, EIC7700_HSP_MSHC1_REG, 16, 2, 0,
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mux_mmc_3mux1_tbl),
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ESWIN_MUX_TBL(EIC7700_HSP_CLK_MUX_SD1_3MUX1, "mux_hsp_sd1_3mux1",
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mux_mmc_3mux1_p, ARRAY_SIZE(mux_mmc_3mux1_p),
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CLK_SET_RATE_PARENT, EIC7700_HSP_MSHC2_REG, 16, 2, 0,
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mux_mmc_3mux1_tbl),
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ESWIN_MUX(EIC7700_HSP_CLK_MUX_EMMC_CQE_2MUX1, "mux_hsp_emmc_cqe_2mux1",
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mux_mmc_2mux1_p, ARRAY_SIZE(mux_mmc_2mux1_p),
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CLK_SET_RATE_PARENT, EIC7700_HSP_MSHC0_REG, 0, 1, 0),
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ESWIN_MUX(EIC7700_HSP_CLK_MUX_SD0_CQE_2MUX1, "mux_hsp_sd0_cqe_2mux1",
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mux_mmc_2mux1_p, ARRAY_SIZE(mux_mmc_2mux1_p),
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CLK_SET_RATE_PARENT, EIC7700_HSP_MSHC1_REG, 0, 1, 0),
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ESWIN_MUX(EIC7700_HSP_CLK_MUX_SD1_CQE_2MUX1, "mux_hsp_sd1_cqe_2mux1",
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mux_mmc_2mux1_p, ARRAY_SIZE(mux_mmc_2mux1_p),
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CLK_SET_RATE_PARENT, EIC7700_HSP_MSHC2_REG, 0, 1, 0),
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};
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static struct eswin_clk_info eic7700_hsp_clks[] = {
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ESWIN_GATE_TYPE(EIC7700_HSP_CLK_GATE_EMMC, "gate_clk_hsp_emmc",
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EIC7700_HSP_CLK_MUX_EMMC_3MUX1,
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CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
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EIC7700_HSP_MSHC0_REG, 24, 0),
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ESWIN_GATE_TYPE(EIC7700_HSP_CLK_GATE_SD0, "gate_clk_hsp_sd0",
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EIC7700_HSP_CLK_MUX_SD0_3MUX1,
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CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
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EIC7700_HSP_MSHC1_REG, 24, 0),
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ESWIN_GATE_TYPE(EIC7700_HSP_CLK_GATE_SD1, "gate_clk_hsp_sd1",
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EIC7700_HSP_CLK_MUX_SD1_3MUX1,
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CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
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EIC7700_HSP_MSHC2_REG, 24, 0),
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};
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static int eic7700_hsp_clk_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct auxiliary_device *adev;
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struct eswin_clock_data *data;
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struct regmap *regmap;
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struct clk_hw *hw;
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int i, ret;
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data = eswin_clk_init(pdev, EIC7700_HSP_NR_CLKS);
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if (IS_ERR(data))
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return dev_err_probe(dev, PTR_ERR(data),
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"failed to get clk data!\n");
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regmap = devm_regmap_init_mmio(dev, data->base,
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&eic7700_hsp_regmap_config);
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if (IS_ERR(regmap))
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return dev_err_probe(dev, PTR_ERR(regmap),
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"failed to get regmap!\n");
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ret = eswin_clk_register_fixed_factor(dev, eic7700_hsp_factor_clks,
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ARRAY_SIZE(eic7700_hsp_factor_clks),
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data);
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if (ret)
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return dev_err_probe(dev, ret,
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"failed to register fixed factor clock\n");
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ret = eswin_clk_register_gate(dev, eic7700_hsp_gate_clks,
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ARRAY_SIZE(eic7700_hsp_gate_clks), data);
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if (ret)
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return dev_err_probe(dev, ret,
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"failed to register gate clock\n");
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ret = eswin_clk_register_mux(dev, eic7700_hsp_mux_clks,
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ARRAY_SIZE(eic7700_hsp_mux_clks),
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data);
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if (ret)
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return dev_err_probe(dev, ret,
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"failed to register mux clock\n");
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ret = eswin_clk_register_clks(dev, eic7700_hsp_clks,
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ARRAY_SIZE(eic7700_hsp_clks), data);
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if (ret)
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return dev_err_probe(dev, ret,
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"failed to register clock\n");
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for (i = 0; i < ARRAY_SIZE(eic7700_hsp_spec_gate_clks); i++) {
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struct eic7700_hsp_clk_gate *gate;
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gate = &eic7700_hsp_spec_gate_clks[i];
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hw = hsp_clk_register_gate(dev, gate->id, gate->name,
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gate->parent_data, gate->flags,
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regmap, gate->offset,
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gate->ref_offset, gate->bit_idx);
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if (IS_ERR(hw))
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return dev_err_probe(dev, PTR_ERR(hw),
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"failed to register gate clock\n");
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data->clk_data.hws[gate->id] = hw;
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}
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ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
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&data->clk_data);
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if (ret)
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return dev_err_probe(dev, ret, "add clk provider failed\n");
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adev = devm_auxiliary_device_create(dev, "hsp-reset", NULL);
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if (!adev)
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return dev_err_probe(dev, -ENODEV,
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"register hsp-reset device failed\n");
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return 0;
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}
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static const struct of_device_id eic7700_hsp_clock_dt_ids[] = {
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{ .compatible = "eswin,eic7700-hspcrg", },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, eic7700_hsp_clock_dt_ids);
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static struct platform_driver eic7700_hsp_clock_driver = {
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.probe = eic7700_hsp_clk_probe,
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.driver = {
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.name = "eic7700-hsp-clock",
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.of_match_table = eic7700_hsp_clock_dt_ids,
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},
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};
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module_platform_driver(eic7700_hsp_clock_driver);
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("Xuyang Dong <dongxuyang@eswincomputing.com>");
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MODULE_DESCRIPTION("ESWIN EIC7700 HSP clock controller driver");
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