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Add a platform driver for the Cix Sky1 AUDSS CRU. The driver maps the CRU registers and registers mux, divider and gate clocks for DSP, SRAM, HDA, DMAC, I2S, mailbox, watchdog and timer blocks. Four SoC-level audio reference clocks are enabled as inputs to the internal clock tree. The driver releases the AUDSS NOC reset, enables runtime PM and instantiates the auxiliary reset device. Signed-off-by: Joakim Zhang <joakim.zhang@cixtech.com> Reviewed-by: Brian Masney <bmasney@redhat.com> Signed-off-by: Brian Masney <bmasney@redhat.com>
17 lines
580 B
Plaintext
17 lines
580 B
Plaintext
# SPDX-License-Identifier: GPL-2.0
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# Audio subsystem clock support for Cixtech SoC family
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menu "Cixtech Audio Subsystem Clock Driver"
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config CLK_SKY1_AUDSS
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tristate "Cixtech Sky1 Audio Subsystem Clock Driver"
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depends on ARCH_CIX || COMPILE_TEST
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select AUXILIARY_BUS
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select REGMAP_MMIO
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select RESET_CONTROLLER
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help
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Support for the Audio Subsystem clock controller present on
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Cixtech Sky1 SoC. This driver provides mux, divider and gate
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clocks for DSP, I2S, HDA and related blocks in the audio
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subsystem. Say M or Y here if you want to build this driver.
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endmenu
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