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c006978163
NPU firmware requires a host-allocated work buffer for hardware contexts. Allocate a 4 MB host buffer and attach it to device during device init. Refactor aie2_alloc_msg_buffer() and aie2_free_msg_buffer() into common helpers by moving them to aie.c and renaming them to amdxdna_alloc_msg_buffer() and amdxdna_free_msg_buffer(), allowing both AIE2 and AIE4 to reuse the implementation. Signed-off-by: Nishad Saraf <nishads@amd.com> Reviewed-by: Mario Limonciello (AMD) <superm1@kernel.org> Signed-off-by: Lizhi Hou <lizhi.hou@amd.com> Link: https://lore.kernel.org/all/20260505160936.3917732-7-lizhi.hou@amd.com/
90 lines
2.4 KiB
C
90 lines
2.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2026, Advanced Micro Devices, Inc.
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*/
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#ifndef _AIE4_PCI_H_
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#define _AIE4_PCI_H_
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#include <linux/device.h>
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#include <linux/iopoll.h>
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#include <linux/pci.h>
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#include "aie.h"
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#include "amdxdna_mailbox.h"
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struct cert_comp {
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struct amdxdna_dev_hdl *ndev;
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u32 msix_idx;
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int irq;
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struct kref kref;
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wait_queue_head_t waitq;
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};
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struct amdxdna_hwctx_priv {
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struct amdxdna_gem_obj *umq_bo;
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u64 *umq_read_index;
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u64 *umq_write_index;
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struct cert_comp *cert_comp;
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u32 hw_ctx_id;
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};
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struct amdxdna_dev_priv {
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const char *npufw_path;
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const char *certfw_path;
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u32 mbox_bar;
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u32 mbox_rbuf_bar;
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u64 mbox_info_off;
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u32 doorbell_off;
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struct aie_bar_off_pair psp_regs_off[PSP_MAX_REGS];
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struct aie_bar_off_pair smu_regs_off[SMU_MAX_REGS];
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};
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struct amdxdna_dev_hdl {
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struct aie_device aie;
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const struct amdxdna_dev_priv *priv;
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void __iomem *mbox_base;
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void __iomem *rbuf_base;
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struct mailbox *mbox;
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u32 partition_id;
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struct xarray cert_comp_xa; /* device level indexed by msix id */
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struct mutex cert_comp_lock; /* protects cert_comp operations*/
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void *work_buf;
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dma_addr_t work_buf_addr;
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u32 work_buf_size;
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};
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/* aie4_message.c */
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int aie4_query_aie_metadata(struct amdxdna_dev_hdl *ndev,
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struct amdxdna_drm_query_aie_metadata *metadata);
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int aie4_suspend_fw(struct amdxdna_dev_hdl *ndev);
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int aie4_attach_work_buffer(struct amdxdna_dev_hdl *ndev);
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/* aie4_ctx.c */
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int aie4_hwctx_init(struct amdxdna_hwctx *hwctx);
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void aie4_hwctx_fini(struct amdxdna_hwctx *hwctx);
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int aie4_cmd_wait(struct amdxdna_hwctx *hwctx, u64 seq, u32 timeout);
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int aie4_hwctx_valid_doorbell(struct amdxdna_client *client, u32 vm_pgoff);
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/* aie4_sriov.c */
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#if IS_ENABLED(CONFIG_PCI_IOV)
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int aie4_sriov_configure(struct amdxdna_dev *xdna, int num_vfs);
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int aie4_sriov_stop(struct amdxdna_dev_hdl *ndev);
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#else
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#define aie4_sriov_configure NULL
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static inline int aie4_sriov_stop(struct amdxdna_dev_hdl *ndev)
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{
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return 0;
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}
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#endif
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extern const struct amdxdna_dev_ops aie4_pf_ops;
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extern const struct amdxdna_dev_ops aie4_vf_ops;
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#endif /* _AIE4_PCI_H_ */
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