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0701c9e17b
Move the VMX interrupt dispatch magic into the x86 core code. This isolates KVM from the FRED/IDT decisions and reduces the amount of EXPORT_SYMBOL_FOR_KVM(). Suggested-by: Sean Christopherson <seanjc@google.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Tested-by: "Verma, Vishal L" <vishal.l.verma@intel.com> Tested-by: Zhao Liu <zhao1.liu@intel.com> Tested-by: Zhao Liu <zhao1.liu@intel.com> Tested-by: Sean Christopherson <seanjc@google.com> Reviewed-by: Binbin Wu <binbin.wu@linxu.intel.com> Acked-by: Sean Christopherson <seanjc@google.com> Link: https://patch.msgid.link/20260508091829.GO3126523@noisy.programming.kicks-ass.net
342 lines
8.7 KiB
ArmAsm
342 lines
8.7 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0 */
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#include <linux/linkage.h>
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#include <asm/asm.h>
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#include <asm/bitsperlong.h>
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#include <asm/kvm_vcpu_regs.h>
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#include <asm/nospec-branch.h>
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#include <asm/percpu.h>
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#include <asm/segment.h>
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#include "kvm-asm-offsets.h"
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#include "run_flags.h"
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#define WORD_SIZE (BITS_PER_LONG / 8)
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#define VCPU_RAX __VCPU_REGS_RAX * WORD_SIZE
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#define VCPU_RCX __VCPU_REGS_RCX * WORD_SIZE
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#define VCPU_RDX __VCPU_REGS_RDX * WORD_SIZE
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#define VCPU_RBX __VCPU_REGS_RBX * WORD_SIZE
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/* Intentionally omit RSP as it's context switched by hardware */
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#define VCPU_RBP __VCPU_REGS_RBP * WORD_SIZE
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#define VCPU_RSI __VCPU_REGS_RSI * WORD_SIZE
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#define VCPU_RDI __VCPU_REGS_RDI * WORD_SIZE
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#ifdef CONFIG_X86_64
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#define VCPU_R8 __VCPU_REGS_R8 * WORD_SIZE
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#define VCPU_R9 __VCPU_REGS_R9 * WORD_SIZE
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#define VCPU_R10 __VCPU_REGS_R10 * WORD_SIZE
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#define VCPU_R11 __VCPU_REGS_R11 * WORD_SIZE
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#define VCPU_R12 __VCPU_REGS_R12 * WORD_SIZE
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#define VCPU_R13 __VCPU_REGS_R13 * WORD_SIZE
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#define VCPU_R14 __VCPU_REGS_R14 * WORD_SIZE
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#define VCPU_R15 __VCPU_REGS_R15 * WORD_SIZE
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#endif
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.section .noinstr.text, "ax"
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/**
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* __vmx_vcpu_run - Run a vCPU via a transition to VMX guest mode
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* @vmx: struct vcpu_vmx *
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* @regs: unsigned long * (to guest registers)
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* @flags: VMX_RUN_VMRESUME: use VMRESUME instead of VMLAUNCH
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* VMX_RUN_SAVE_SPEC_CTRL: save guest SPEC_CTRL into vmx->spec_ctrl
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* VMX_RUN_CLEAR_CPU_BUFFERS_FOR_MMIO: vCPU can access host MMIO
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*
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* Returns:
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* 0 on VM-Exit, 1 on VM-Fail
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*/
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SYM_FUNC_START(__vmx_vcpu_run)
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push %_ASM_BP
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mov %_ASM_SP, %_ASM_BP
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#ifdef CONFIG_X86_64
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push %r15
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push %r14
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push %r13
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push %r12
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#else
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push %edi
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push %esi
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#endif
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push %_ASM_BX
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/* Save @vmx for SPEC_CTRL handling */
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push %_ASM_ARG1
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/* Save @flags (used for VMLAUNCH vs. VMRESUME and mitigations). */
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push %_ASM_ARG3
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/*
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* Save @regs, _ASM_ARG2 may be modified by vmx_update_host_rsp() and
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* @regs is needed after VM-Exit to save the guest's register values.
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*/
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push %_ASM_ARG2
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lea (%_ASM_SP), %_ASM_ARG2
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call vmx_update_host_rsp
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ALTERNATIVE "jmp .Lspec_ctrl_done", "", X86_FEATURE_MSR_SPEC_CTRL
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/*
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* SPEC_CTRL handling: if the guest's SPEC_CTRL value differs from the
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* host's, write the MSR.
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*
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* IMPORTANT: To avoid RSB underflow attacks and any other nastiness,
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* there must not be any returns or indirect branches between this code
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* and vmentry.
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*/
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mov 2*WORD_SIZE(%_ASM_SP), %_ASM_DI
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#ifdef CONFIG_X86_64
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mov VMX_spec_ctrl(%rdi), %rdx
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cmp PER_CPU_VAR(x86_spec_ctrl_current), %rdx
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je .Lspec_ctrl_done
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movl %edx, %eax
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shr $32, %rdx
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#else
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mov VMX_spec_ctrl(%edi), %eax
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mov PER_CPU_VAR(x86_spec_ctrl_current), %ecx
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xor %eax, %ecx
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mov VMX_spec_ctrl + 4(%edi), %edx
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mov PER_CPU_VAR(x86_spec_ctrl_current + 4), %edi
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xor %edx, %edi
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or %edi, %ecx
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je .Lspec_ctrl_done
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#endif
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mov $MSR_IA32_SPEC_CTRL, %ecx
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wrmsr
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.Lspec_ctrl_done:
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/*
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* Since vmentry is serializing on affected CPUs, there's no need for
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* an LFENCE to stop speculation from skipping the wrmsr.
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*/
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/* Load @regs to RAX. */
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mov (%_ASM_SP), %_ASM_AX
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/* Load guest registers. Don't clobber flags. */
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mov VCPU_RCX(%_ASM_AX), %_ASM_CX
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mov VCPU_RDX(%_ASM_AX), %_ASM_DX
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mov VCPU_RBX(%_ASM_AX), %_ASM_BX
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mov VCPU_RBP(%_ASM_AX), %_ASM_BP
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mov VCPU_RSI(%_ASM_AX), %_ASM_SI
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mov VCPU_RDI(%_ASM_AX), %_ASM_DI
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#ifdef CONFIG_X86_64
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mov VCPU_R8 (%_ASM_AX), %r8
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mov VCPU_R9 (%_ASM_AX), %r9
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mov VCPU_R10(%_ASM_AX), %r10
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mov VCPU_R11(%_ASM_AX), %r11
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mov VCPU_R12(%_ASM_AX), %r12
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mov VCPU_R13(%_ASM_AX), %r13
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mov VCPU_R14(%_ASM_AX), %r14
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mov VCPU_R15(%_ASM_AX), %r15
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#endif
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/* Load guest RAX. This kills the @regs pointer! */
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mov VCPU_RAX(%_ASM_AX), %_ASM_AX
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/*
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* Note, ALTERNATIVE_2 works in reverse order. If CLEAR_CPU_BUF_VM is
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* enabled, do VERW unconditionally. If CPU_BUF_VM_MMIO is enabled,
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* check @flags to see if the vCPU has access to host MMIO, and if so,
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* do VERW. Else, do nothing (no mitigations needed/enabled).
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*/
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ALTERNATIVE_2 "", \
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__stringify(testl $VMX_RUN_CLEAR_CPU_BUFFERS_FOR_MMIO, WORD_SIZE(%_ASM_SP); \
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jz .Lskip_mmio_verw; \
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VERW; \
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.Lskip_mmio_verw:), \
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X86_FEATURE_CLEAR_CPU_BUF_VM_MMIO, \
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__stringify(VERW), X86_FEATURE_CLEAR_CPU_BUF_VM
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/* Check @flags to see if VMLAUNCH or VMRESUME is needed. */
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testl $VMX_RUN_VMRESUME, WORD_SIZE(%_ASM_SP)
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jz .Lvmlaunch
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/*
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* After a successful VMRESUME/VMLAUNCH, control flow "magically"
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* resumes below at 'vmx_vmexit' due to the VMCS HOST_RIP setting.
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* So this isn't a typical function and objtool needs to be told to
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* save the unwind state here and restore it below.
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*/
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UNWIND_HINT_SAVE
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/*
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* If VMRESUME/VMLAUNCH and corresponding vmexit succeed, execution resumes at
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* the 'vmx_vmexit' label below.
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*/
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.Lvmresume:
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vmresume
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jmp .Lvmfail
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.Lvmlaunch:
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vmlaunch
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jmp .Lvmfail
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_ASM_EXTABLE(.Lvmresume, .Lfixup)
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_ASM_EXTABLE(.Lvmlaunch, .Lfixup)
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SYM_INNER_LABEL_ALIGN(vmx_vmexit, SYM_L_GLOBAL)
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/* Restore unwind state from before the VMRESUME/VMLAUNCH. */
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UNWIND_HINT_RESTORE
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ENDBR
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/* Temporarily save guest's RAX. */
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push %_ASM_AX
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/* Reload @regs to RAX. */
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mov WORD_SIZE(%_ASM_SP), %_ASM_AX
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/* Save all guest registers, including RAX from the stack */
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pop VCPU_RAX(%_ASM_AX)
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mov %_ASM_CX, VCPU_RCX(%_ASM_AX)
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mov %_ASM_DX, VCPU_RDX(%_ASM_AX)
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mov %_ASM_BX, VCPU_RBX(%_ASM_AX)
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mov %_ASM_BP, VCPU_RBP(%_ASM_AX)
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mov %_ASM_SI, VCPU_RSI(%_ASM_AX)
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mov %_ASM_DI, VCPU_RDI(%_ASM_AX)
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#ifdef CONFIG_X86_64
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mov %r8, VCPU_R8 (%_ASM_AX)
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mov %r9, VCPU_R9 (%_ASM_AX)
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mov %r10, VCPU_R10(%_ASM_AX)
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mov %r11, VCPU_R11(%_ASM_AX)
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mov %r12, VCPU_R12(%_ASM_AX)
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mov %r13, VCPU_R13(%_ASM_AX)
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mov %r14, VCPU_R14(%_ASM_AX)
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mov %r15, VCPU_R15(%_ASM_AX)
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#endif
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/* Clear return value to indicate VM-Exit (as opposed to VM-Fail). */
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xor %ebx, %ebx
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.Lclear_regs:
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/* Discard @regs. The register is irrelevant, it just can't be RBX. */
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pop %_ASM_AX
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/*
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* Clear all general purpose registers except RSP and RBX to prevent
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* speculative use of the guest's values, even those that are reloaded
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* via the stack. In theory, an L1 cache miss when restoring registers
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* could lead to speculative execution with the guest's values.
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* Zeroing XORs are dirt cheap, i.e. the extra paranoia is essentially
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* free. RSP and RBX are exempt as RSP is restored by hardware during
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* VM-Exit and RBX is explicitly loaded with 0 or 1 to hold the return
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* value.
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*/
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xor %eax, %eax
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xor %ecx, %ecx
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xor %edx, %edx
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xor %ebp, %ebp
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xor %esi, %esi
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xor %edi, %edi
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#ifdef CONFIG_X86_64
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xor %r8d, %r8d
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xor %r9d, %r9d
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xor %r10d, %r10d
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xor %r11d, %r11d
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xor %r12d, %r12d
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xor %r13d, %r13d
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xor %r14d, %r14d
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xor %r15d, %r15d
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#endif
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/*
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* IMPORTANT: RSB filling and SPEC_CTRL handling must be done before
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* the first unbalanced RET after vmexit!
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*
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* For retpoline or IBRS, RSB filling is needed to prevent poisoned RSB
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* entries and (in some cases) RSB underflow.
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*
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* eIBRS has its own protection against poisoned RSB, so it doesn't
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* need the RSB filling sequence. But it does need to be enabled, and a
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* single call to retire, before the first unbalanced RET.
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*/
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FILL_RETURN_BUFFER %_ASM_CX, RSB_CLEAR_LOOPS, X86_FEATURE_RSB_VMEXIT,\
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X86_FEATURE_RSB_VMEXIT_LITE
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pop %_ASM_ARG2 /* @flags */
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pop %_ASM_ARG1 /* @vmx */
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call vmx_spec_ctrl_restore_host
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CLEAR_BRANCH_HISTORY_VMEXIT
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/* Put return value in AX */
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mov %_ASM_BX, %_ASM_AX
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pop %_ASM_BX
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#ifdef CONFIG_X86_64
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pop %r12
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pop %r13
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pop %r14
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pop %r15
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#else
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pop %esi
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pop %edi
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#endif
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pop %_ASM_BP
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RET
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.Lfixup:
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cmpb $0, _ASM_RIP(virt_rebooting)
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jne .Lvmfail
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ud2
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.Lvmfail:
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/* VM-Fail: set return value to 1 */
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mov $1, %_ASM_BX
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jmp .Lclear_regs
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SYM_FUNC_END(__vmx_vcpu_run)
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#ifndef CONFIG_CC_HAS_ASM_GOTO_OUTPUT
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/**
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* vmread_error_trampoline - Trampoline from inline asm to vmread_error()
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* @field: VMCS field encoding that failed
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* @fault: %true if the VMREAD faulted, %false if it failed
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*
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* Save and restore volatile registers across a call to vmread_error(). Note,
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* all parameters are passed on the stack.
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*/
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SYM_FUNC_START(vmread_error_trampoline)
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push %_ASM_BP
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mov %_ASM_SP, %_ASM_BP
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push %_ASM_AX
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push %_ASM_CX
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push %_ASM_DX
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#ifdef CONFIG_X86_64
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push %rdi
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push %rsi
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push %r8
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push %r9
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push %r10
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push %r11
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#endif
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/* Load @field and @fault to arg1 and arg2 respectively. */
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mov 3*WORD_SIZE(%_ASM_BP), %_ASM_ARG2
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mov 2*WORD_SIZE(%_ASM_BP), %_ASM_ARG1
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call vmread_error_trampoline2
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/* Zero out @fault, which will be popped into the result register. */
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_ASM_MOV $0, 3*WORD_SIZE(%_ASM_BP)
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#ifdef CONFIG_X86_64
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pop %r11
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pop %r10
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pop %r9
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pop %r8
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pop %rsi
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pop %rdi
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#endif
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pop %_ASM_DX
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pop %_ASM_CX
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pop %_ASM_AX
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pop %_ASM_BP
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RET
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SYM_FUNC_END(vmread_error_trampoline)
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#endif
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