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For vCPUs with a mediated vPMU, disable interception of counter MSRs for PMCs that are exposed to the guest, and for GLOBAL_CTRL and related MSRs if they are fully supported according to the vCPU model, i.e. if the MSRs and all bits supported by hardware exist from the guest's point of view. Do NOT passthrough event selector or fixed counter control MSRs, so that KVM can enforce userspace-defined event filters, e.g. to prevent use of AnyThread events (which is unfortunately a setting in the fixed counter control MSR). Defer support for nested passthrough of mediated PMU MSRs to the future, as the logic for nested MSR interception is unfortunately vendor specific. Suggested-by: Sean Christopherson <seanjc@google.com> Co-developed-by: Mingwei Zhang <mizhang@google.com> Signed-off-by: Mingwei Zhang <mizhang@google.com> Co-developed-by: Sandipan Das <sandipan.das@amd.com> Signed-off-by: Sandipan Das <sandipan.das@amd.com> Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com> [sean: squash patches, massage changelog, refresh VMX MSRs on filter change] Tested-by: Xudong Hao <xudong.hao@intel.com> Tested-by: Manali Shukla <manali.shukla@amd.com> Link: https://patch.msgid.link/20251206001720.468579-23-seanjc@google.com Signed-off-by: Sean Christopherson <seanjc@google.com>
44 lines
1.1 KiB
C
44 lines
1.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __KVM_X86_VMX_PMU_INTEL_H
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#define __KVM_X86_VMX_PMU_INTEL_H
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#include <linux/kvm_host.h>
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#include "cpuid.h"
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static inline u64 vcpu_get_perf_capabilities(struct kvm_vcpu *vcpu)
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{
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if (!guest_cpu_cap_has(vcpu, X86_FEATURE_PDCM))
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return 0;
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return vcpu->arch.perf_capabilities;
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}
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static inline bool fw_writes_is_enabled(struct kvm_vcpu *vcpu)
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{
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return (vcpu_get_perf_capabilities(vcpu) & PERF_CAP_FW_WRITES) != 0;
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}
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bool intel_pmu_lbr_is_enabled(struct kvm_vcpu *vcpu);
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int intel_pmu_create_guest_lbr_event(struct kvm_vcpu *vcpu);
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struct lbr_desc {
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/* Basic info about guest LBR records. */
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struct x86_pmu_lbr records;
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/*
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* Emulate LBR feature via passthrough LBR registers when the
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* per-vcpu guest LBR event is scheduled on the current pcpu.
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*
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* The records may be inaccurate if the host reclaims the LBR.
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*/
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struct perf_event *event;
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/* True if LBRs are marked as not intercepted in the MSR bitmap */
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bool msr_passthrough;
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};
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extern struct x86_pmu_lbr vmx_lbr_caps;
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#endif /* __KVM_X86_VMX_PMU_INTEL_H */
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