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9183c97e7e
Forgot to do that during the Secure AVIC review. :-\ No functional changes. Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Tom Lendacky <thomas.lendacky@amd.com> Link: https://patch.msgid.link/20260119141310.29605-1-bp@kernel.org
120 lines
3.4 KiB
C
120 lines
3.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __X86_COCO_SEV_INTERNAL_H__
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#define __X86_COCO_SEV_INTERNAL_H__
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#define DR7_RESET_VALUE 0x400
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extern u64 sev_hv_features;
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extern u64 sev_secrets_pa;
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/* #VC handler runtime per-CPU data */
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struct sev_es_runtime_data {
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struct ghcb ghcb_page;
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/*
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* Reserve one page per CPU as backup storage for the unencrypted GHCB.
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* It is needed when an NMI happens while the #VC handler uses the real
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* GHCB, and the NMI handler itself is causing another #VC exception. In
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* that case the GHCB content of the first handler needs to be backed up
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* and restored.
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*/
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struct ghcb backup_ghcb;
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/*
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* Mark the per-cpu GHCBs as in-use to detect nested #VC exceptions.
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* There is no need for it to be atomic, because nothing is written to
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* the GHCB between the read and the write of ghcb_active. So it is safe
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* to use it when a nested #VC exception happens before the write.
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*
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* This is necessary for example in the #VC->NMI->#VC case when the NMI
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* happens while the first #VC handler uses the GHCB. When the NMI code
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* raises a second #VC handler it might overwrite the contents of the
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* GHCB written by the first handler. To avoid this the content of the
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* GHCB is saved and restored when the GHCB is detected to be in use
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* already.
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*/
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bool ghcb_active;
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bool backup_ghcb_active;
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/*
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* Cached DR7 value - write it on DR7 writes and return it on reads.
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* That value will never make it to the real hardware DR7 as debugging
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* is currently unsupported in SEV-ES guests.
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*/
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unsigned long dr7;
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};
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struct ghcb_state {
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struct ghcb *ghcb;
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};
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extern struct svsm_ca boot_svsm_ca_page;
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struct ghcb *__sev_get_ghcb(struct ghcb_state *state);
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void __sev_put_ghcb(struct ghcb_state *state);
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DECLARE_PER_CPU(struct sev_es_runtime_data*, runtime_data);
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DECLARE_PER_CPU(struct sev_es_save_area *, sev_vmsa);
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void early_set_pages_state(unsigned long vaddr, unsigned long paddr,
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unsigned long npages, const struct psc_desc *desc);
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DECLARE_PER_CPU(struct svsm_ca *, svsm_caa);
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DECLARE_PER_CPU(u64, svsm_caa_pa);
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extern u64 boot_svsm_caa_pa;
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enum es_result verify_exception_info(struct ghcb *ghcb, struct es_em_ctxt *ctxt);
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void vc_forward_exception(struct es_em_ctxt *ctxt);
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void svsm_pval_pages(struct snp_psc_desc *desc);
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int svsm_perform_call_protocol(struct svsm_call *call);
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bool snp_svsm_vtpm_probe(void);
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static inline u64 sev_es_rd_ghcb_msr(void)
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{
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return native_rdmsrq(MSR_AMD64_SEV_ES_GHCB);
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}
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static __always_inline void sev_es_wr_ghcb_msr(u64 val)
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{
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u32 low, high;
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low = (u32)(val);
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high = (u32)(val >> 32);
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native_wrmsr(MSR_AMD64_SEV_ES_GHCB, low, high);
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}
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enum es_result __vc_handle_msr(struct ghcb *ghcb, struct es_em_ctxt *ctxt, bool write);
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u64 get_hv_features(void);
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const struct snp_cpuid_table *snp_cpuid_get_table(void);
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static inline struct svsm_ca *svsm_get_caa(void)
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{
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if (sev_cfg.use_cas)
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return this_cpu_read(svsm_caa);
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else
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return rip_rel_ptr(&boot_svsm_ca_page);
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}
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static inline u64 svsm_get_caa_pa(void)
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{
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if (sev_cfg.use_cas)
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return this_cpu_read(svsm_caa_pa);
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else
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return boot_svsm_caa_pa;
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}
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static inline void __pval_terminate(u64 pfn, bool action, unsigned int page_size,
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int ret, u64 svsm_ret)
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{
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WARN(1, "PVALIDATE failure: pfn: 0x%llx, action: %u, size: %u, ret: %d, svsm_ret: 0x%llx\n",
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pfn, action, page_size, ret, svsm_ret);
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sev_es_terminate(SEV_TERM_SET_LINUX, GHCB_TERM_PVALIDATE);
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}
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#endif /* __X86_COCO_SEV_INTERNAL_H__ */
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