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'arch_calc_vm_prot_bits' is implemented on risc-v to return VM_READ | VM_WRITE if PROT_WRITE is specified. Similarly 'riscv_sys_mmap' is updated to convert all incoming PROT_WRITE to (PROT_WRITE | PROT_READ). This is to make sure that any existing apps using PROT_WRITE still work. Earlier 'protection_map[VM_WRITE]' used to pick read-write PTE encodings. Now 'protection_map[VM_WRITE]' will always pick PAGE_SHADOWSTACK PTE encodings for shadow stack. The above changes ensure that existing apps continue to work because underneath, the kernel will be picking 'protection_map[VM_WRITE|VM_READ]' PTE encodings. Reviewed-by: Zong Li <zong.li@sifive.com> Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com> Signed-off-by: Deepak Gupta <debug@rivosinc.com> Tested-by: Andreas Korb <andreas.korb@aisec.fraunhofer.de> # QEMU, custom CVA6 Tested-by: Valentin Haudiquet <valentin.haudiquet@canonical.com> Link: https://patch.msgid.link/20251112-v5_user_cfi_series-v23-6-b55691eacf4f@rivosinc.com Signed-off-by: Paul Walmsley <pjw@kernel.org>
86 lines
2.8 KiB
C
86 lines
2.8 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2012 Regents of the University of California
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* Copyright (C) 2014 Darius Rad <darius@bluespec.com>
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* Copyright (C) 2017 SiFive
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*/
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#include <linux/syscalls.h>
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#include <asm/cacheflush.h>
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#include <asm-generic/mman-common.h>
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static long riscv_sys_mmap(unsigned long addr, unsigned long len,
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unsigned long prot, unsigned long flags,
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unsigned long fd, unsigned long offset,
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unsigned long page_shift_offset)
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{
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if (unlikely(offset & (~PAGE_MASK >> page_shift_offset)))
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return -EINVAL;
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/*
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* If PROT_WRITE is specified then extend that to PROT_READ
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* protection_map[VM_WRITE] is now going to select shadow stack encodings.
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* So specifying PROT_WRITE actually should select protection_map [VM_WRITE | VM_READ]
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* If user wants to create shadow stack then they should use `map_shadow_stack` syscall.
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*/
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if (unlikely((prot & PROT_WRITE) && !(prot & PROT_READ)))
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prot |= PROT_READ;
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return ksys_mmap_pgoff(addr, len, prot, flags, fd,
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offset >> (PAGE_SHIFT - page_shift_offset));
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}
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#ifdef CONFIG_64BIT
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SYSCALL_DEFINE6(mmap, unsigned long, addr, unsigned long, len,
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unsigned long, prot, unsigned long, flags,
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unsigned long, fd, unsigned long, offset)
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{
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return riscv_sys_mmap(addr, len, prot, flags, fd, offset, 0);
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}
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#endif
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#if defined(CONFIG_32BIT) || defined(CONFIG_COMPAT)
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SYSCALL_DEFINE6(mmap2, unsigned long, addr, unsigned long, len,
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unsigned long, prot, unsigned long, flags,
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unsigned long, fd, unsigned long, offset)
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{
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/*
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* Note that the shift for mmap2 is constant (12),
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* regardless of PAGE_SIZE
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*/
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return riscv_sys_mmap(addr, len, prot, flags, fd, offset, 12);
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}
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#endif
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/*
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* Allows the instruction cache to be flushed from userspace. Despite RISC-V
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* having a direct 'fence.i' instruction available to userspace (which we
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* can't trap!), that's not actually viable when running on Linux because the
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* kernel might schedule a process on another hart. There is no way for
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* userspace to handle this without invoking the kernel (as it doesn't know the
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* thread->hart mappings), so we've defined a RISC-V specific system call to
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* flush the instruction cache.
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*
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* sys_riscv_flush_icache() is defined to flush the instruction cache over an
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* address range, with the flush applying to either all threads or just the
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* caller. We don't currently do anything with the address range, that's just
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* in there for forwards compatibility.
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*/
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SYSCALL_DEFINE3(riscv_flush_icache, uintptr_t, start, uintptr_t, end,
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uintptr_t, flags)
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{
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/* Check the reserved flags. */
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if (unlikely(flags & ~SYS_RISCV_FLUSH_ICACHE_ALL))
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return -EINVAL;
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flush_icache_mm(current->mm, flags & SYS_RISCV_FLUSH_ICACHE_LOCAL);
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return 0;
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}
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/* Not defined using SYSCALL_DEFINE0 to avoid error injection */
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asmlinkage long __riscv_sys_ni_syscall(const struct pt_regs *__unused)
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{
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return -ENOSYS;
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}
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