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7d7c2d1c48
Fix various typos in RISC-V architecture code and comments. The following changes are included: - arch/riscv/errata/thead/errata.c: "futher" → "further" - arch/riscv/include/asm/atomic.h: "therefor" → "therefore", "arithmatic" → "arithmetic" - arch/riscv/include/asm/elf.h: "availiable" → "available", "coorespends" → "corresponds" - arch/riscv/include/asm/processor.h: "requries" → "is required" - arch/riscv/include/asm/thread_info.h: "returing" → "returning" - arch/riscv/kernel/acpi.c: "compliancy" → "compliance" - arch/riscv/kernel/ftrace.c: "therefor" → "therefore" - arch/riscv/kernel/head.S: "intruction" → "instruction" - arch/riscv/kernel/mcount-dyn.S: "localtion → "location" - arch/riscv/kernel/module-sections.c: "maxinum" → "maximum" - arch/riscv/kernel/probes/kprobes.c: "reenabled" → "re-enabled" - arch/riscv/kernel/probes/uprobes.c: "probbed" → "probed" - arch/riscv/kernel/soc.c: "extremly" → "extremely" - arch/riscv/kernel/suspend.c: "incosistent" → "inconsistent" - arch/riscv/kvm/tlb.c: "cahce" → "cache" - arch/riscv/kvm/vcpu_pmu.c: "indicies" → "indices" - arch/riscv/lib/csum.c: "implmentations" → "implementations" - arch/riscv/lib/memmove.S: "ammount" → "amount" - arch/riscv/mm/cacheflush.c: "visable" → "visible" - arch/riscv/mm/physaddr.c: "aginst" → "against" Signed-off-by: Sean Chang <seanwascoding@gmail.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20260212163325.60389-1-seanwascoding@gmail.com Signed-off-by: Paul Walmsley <pjw@kernel.org>
128 lines
3.4 KiB
C
128 lines
3.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2009 Chen Liqin <liqin.chen@sunplusct.com>
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* Copyright (C) 2012 Regents of the University of California
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* Copyright (C) 2017 SiFive
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*/
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#ifndef _ASM_RISCV_THREAD_INFO_H
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#define _ASM_RISCV_THREAD_INFO_H
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#include <asm/page.h>
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#include <linux/const.h>
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#include <linux/sizes.h>
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/* thread information allocation */
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#ifdef CONFIG_KASAN
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#define KASAN_STACK_ORDER 1
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#else
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#define KASAN_STACK_ORDER 0
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#endif
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#define THREAD_SIZE_ORDER (CONFIG_THREAD_SIZE_ORDER + KASAN_STACK_ORDER)
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#define THREAD_SIZE (PAGE_SIZE << THREAD_SIZE_ORDER)
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/*
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* By aligning VMAP'd stacks to 2 * THREAD_SIZE, we can detect overflow by
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* checking sp & (1 << THREAD_SHIFT), which we can do cheaply in the entry
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* assembly.
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*/
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#ifdef CONFIG_VMAP_STACK
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#define THREAD_ALIGN (2 * THREAD_SIZE)
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#else
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#define THREAD_ALIGN THREAD_SIZE
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#endif
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#define THREAD_SHIFT (PAGE_SHIFT + THREAD_SIZE_ORDER)
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#define OVERFLOW_STACK_SIZE SZ_4K
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#define IRQ_STACK_SIZE THREAD_SIZE
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#ifndef __ASSEMBLER__
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#include <asm/processor.h>
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#include <asm/csr.h>
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/*
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* low level task data that entry.S needs immediate access to
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* - this struct should fit entirely inside of one cache line
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* - if the members of this struct changes, the assembly constants
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* in asm-offsets.c must be updated accordingly
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* - thread_info is included in task_struct at an offset of 0. This means that
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* tp points to both thread_info and task_struct.
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*/
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struct thread_info {
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unsigned long flags; /* low level flags */
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int preempt_count; /* 0=>preemptible, <0=>BUG */
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/*
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* These stack pointers are overwritten on every system call or
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* exception. SP is also saved to the stack it can be recovered when
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* overwritten.
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*/
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long kernel_sp; /* Kernel stack pointer */
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long user_sp; /* User stack pointer */
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int cpu;
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unsigned long syscall_work; /* SYSCALL_WORK_ flags */
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#ifdef CONFIG_SHADOW_CALL_STACK
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void *scs_base;
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void *scs_sp;
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#endif
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#ifdef CONFIG_64BIT
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/*
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* Used in handle_exception() to save a0, a1 and a2 before knowing if we
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* can access the kernel stack.
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*/
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unsigned long a0, a1, a2;
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#endif
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#ifdef CONFIG_RISCV_USER_CFI
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struct cfi_state user_cfi_state;
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#endif
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};
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#ifdef CONFIG_SHADOW_CALL_STACK
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#define INIT_SCS \
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.scs_base = init_shadow_call_stack, \
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.scs_sp = init_shadow_call_stack,
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#else
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#define INIT_SCS
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#endif
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/*
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* macros/functions for gaining access to the thread information structure
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*
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* preempt_count needs to be 1 initially, until the scheduler is functional.
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*/
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#define INIT_THREAD_INFO(tsk) \
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{ \
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.flags = 0, \
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.preempt_count = INIT_PREEMPT_COUNT, \
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INIT_SCS \
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}
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void arch_release_task_struct(struct task_struct *tsk);
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int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src);
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#endif /* !__ASSEMBLER__ */
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/*
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* thread information flags
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* - these are process state flags that various assembly files may need to
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* access
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* - pending work-to-be-done flags are in lowest half-word
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* - other flags in upper half-word(s)
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*/
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/*
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* Tell the generic TIF infrastructure which bits riscv supports
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*/
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#define HAVE_TIF_NEED_RESCHED_LAZY
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#define HAVE_TIF_RESTORE_SIGMASK
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#include <asm-generic/thread_info_tif.h>
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#define TIF_32BIT 16 /* compat-mode 32bit process */
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#define TIF_RISCV_V_DEFER_RESTORE 17 /* restore Vector before returning to user */
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#define _TIF_RISCV_V_DEFER_RESTORE BIT(TIF_RISCV_V_DEFER_RESTORE)
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#endif /* _ASM_RISCV_THREAD_INFO_H */
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