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326ba66db9
Add support for the srmcfg CSR defined in the Ssqosid ISA extension. The CSR contains two fields: - Resource Control ID (RCID) for resource allocation - Monitoring Counter ID (MCID) for tracking resource usage Requests from a hart to shared resources are tagged with these IDs, allowing resource usage to be associated with the running task. Add a srmcfg field to thread_struct with the same format as the CSR. The context-switch path writes the field to the CSR, and resctrl_arch_set_closid_rmid() updates it when a task is assigned to a resctrl control or monitoring group. A per-cpu cpu_srmcfg_default holds the default srmcfg for each CPU, set by resctrl_arch_set_cpu_default_closid_rmid() on CPU group assignment. On context switch, RCID and MCID inherit from the CPU default independently: a task whose thread RCID field is zero takes the CPU default's RCID, and likewise for MCID. A per-cpu cpu_srmcfg variable mirrors the CSR state to avoid redundant writes. L1D-hot memory access is faster than a CSR read and avoids traps under virtualization. Link: https://github.com/riscv/riscv-ssqosid/releases/tag/v1.0 Assisted-by: Claude:claude-opus-4-7 Co-developed-by: Kornel Dulęba <mindal@semihalf.com> Signed-off-by: Kornel Dulęba <mindal@semihalf.com> Signed-off-by: Drew Fustini <fustini@kernel.org> Link: https://patch.msgid.link/20260729-dfustini-atl-sc-cbqri-dt-v6-3-7c22b05d461b@kernel.org Signed-off-by: Paul Walmsley <pjw@kernel.org>
75 lines
2.1 KiB
C
75 lines
2.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_RISCV_QOS_H
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#define _ASM_RISCV_QOS_H
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#include <linux/percpu-defs.h>
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#ifdef CONFIG_RISCV_ISA_SSQOSID
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#include <linux/bitfield.h>
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#include <linux/cpufeature.h>
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#include <linux/sched.h>
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#include <asm/csr.h>
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#include <asm/hwcap.h>
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/* cached value of srmcfg csr for each cpu */
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DECLARE_PER_CPU(u32, cpu_srmcfg);
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/* default srmcfg value for each cpu, set via resctrl cpu assignment */
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DECLARE_PER_CPU(u32, cpu_srmcfg_default);
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static inline void __switch_to_srmcfg(struct task_struct *next)
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{
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u32 thread_srmcfg, default_srmcfg;
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thread_srmcfg = READ_ONCE(next->thread.srmcfg);
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default_srmcfg = __this_cpu_read(cpu_srmcfg_default);
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/*
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* RCID and MCID inherit from cpu_srmcfg_default independently.
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* RESCTRL_RESERVED_CLOSID and RESCTRL_RESERVED_RMID are both 0, so a
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* zero field means "unassigned" and takes the CPU default.
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*/
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if (thread_srmcfg == 0) {
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thread_srmcfg = default_srmcfg;
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} else {
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u32 rcid = FIELD_GET(SRMCFG_RCID_MASK, thread_srmcfg);
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u32 mcid = FIELD_GET(SRMCFG_MCID_MASK, thread_srmcfg);
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if (rcid == 0 || mcid == 0) {
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if (rcid == 0)
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rcid = FIELD_GET(SRMCFG_RCID_MASK, default_srmcfg);
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if (mcid == 0)
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mcid = FIELD_GET(SRMCFG_MCID_MASK, default_srmcfg);
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thread_srmcfg = FIELD_PREP(SRMCFG_RCID_MASK, rcid) |
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FIELD_PREP(SRMCFG_MCID_MASK, mcid);
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}
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}
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if (thread_srmcfg != __this_cpu_read(cpu_srmcfg)) {
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/*
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* No fence around the csrw. Ssqosid is silent on srmcfg
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* ordering versus memory accesses, so a few accesses at the
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* switch boundary may carry the previous RCID/MCID. The
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* tagging inaccuracy is bounded and acceptable for QoS.
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*/
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__this_cpu_write(cpu_srmcfg, thread_srmcfg);
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csr_write(CSR_SRMCFG, thread_srmcfg);
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}
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}
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static __always_inline bool has_srmcfg(void)
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{
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return riscv_has_extension_unlikely(RISCV_ISA_EXT_SSQOSID);
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}
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#else /* ! CONFIG_RISCV_ISA_SSQOSID */
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struct task_struct;
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static __always_inline bool has_srmcfg(void) { return false; }
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static inline void __switch_to_srmcfg(struct task_struct *next) { }
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#endif /* CONFIG_RISCV_ISA_SSQOSID */
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#endif /* _ASM_RISCV_QOS_H */
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