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462a94fb8a
We've run out of bits to describe RISC-V ISA extensions in our initial hwprobe key, RISCV_HWPROBE_KEY_IMA_EXT_0. So, let's add RISCV_HWPROBE_KEY_IMA_EXT_1, along with the framework to set the appropriate hwprobe tuple, and add testing for it. Based on a suggestion from Andrew Jones <andrew.jones@oss.qualcomm.com>, also fix the documentation for RISCV_HWPROBE_KEY_IMA_EXT_0. Reviewed-by: Andrew Jones <andrew.jones@oss.qualcomm.com> Signed-off-by: Paul Walmsley <pjw@kernel.org>
54 lines
1.3 KiB
C
54 lines
1.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
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/*
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* Copyright 2023-2024 Rivos, Inc
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*/
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#ifndef _ASM_HWPROBE_H
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#define _ASM_HWPROBE_H
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#include <uapi/asm/hwprobe.h>
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#define RISCV_HWPROBE_MAX_KEY 16
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static inline bool riscv_hwprobe_key_is_valid(__s64 key)
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{
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return key >= 0 && key <= RISCV_HWPROBE_MAX_KEY;
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}
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static inline bool hwprobe_key_is_bitmask(__s64 key)
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{
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switch (key) {
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case RISCV_HWPROBE_KEY_BASE_BEHAVIOR:
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case RISCV_HWPROBE_KEY_IMA_EXT_0:
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case RISCV_HWPROBE_KEY_IMA_EXT_1:
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case RISCV_HWPROBE_KEY_CPUPERF_0:
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case RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0:
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case RISCV_HWPROBE_KEY_VENDOR_EXT_MIPS_0:
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case RISCV_HWPROBE_KEY_VENDOR_EXT_SIFIVE_0:
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return true;
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}
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return false;
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}
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static inline bool riscv_hwprobe_pair_cmp(struct riscv_hwprobe *pair,
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struct riscv_hwprobe *other_pair)
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{
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if (pair->key != other_pair->key)
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return false;
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if (hwprobe_key_is_bitmask(pair->key))
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return (pair->value & other_pair->value) == other_pair->value;
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return pair->value == other_pair->value;
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}
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#ifdef CONFIG_MMU
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void riscv_hwprobe_register_async_probe(void);
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void riscv_hwprobe_complete_async_probe(void);
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#else
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static inline void riscv_hwprobe_register_async_probe(void) {}
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static inline void riscv_hwprobe_complete_async_probe(void) {}
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#endif
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#endif
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