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The RISC-V Bit-manipulation Extension for Cryptography (Zbkb) provides the 'brev8' instruction, which reverses the bits within each byte. Combined with the 'rev8' instruction (from Zbb or Zbkb), which reverses the byte order of a register, we can efficiently implement 16-bit, 32-bit, and (on RV64) 64-bit bit reversal. This is significantly faster than the default software table-lookup implementation in lib/bitrev.c, as it replaces memory accesses and multiple arithmetic operations with just two or three hardware instructions. Select HAVE_ARCH_BITREVERSE as well as GENERIC_BITREVERSE, and provide <asm/bitrev.h> to utilize these instructions when the Zbkb extension is available at runtime via the alternatives mechanism. [Yury: select the options conditionally on BITREVERSE] Link: https://docs.riscv.org/reference/isa/unpriv/b-st-ext.html Suggested-by: David Laight <david.laight.linux@gmail.com> Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> Signed-off-by: Yury Norov <ynorov@nvidia.com>
52 lines
1.0 KiB
C
52 lines
1.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __ASM_BITREV_H
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#define __ASM_BITREV_H
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#include <linux/types.h>
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#include <asm/cpufeature-macros.h>
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#include <asm/hwcap.h>
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#include <asm-generic/bitops/__bitrev.h>
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static __always_inline __attribute_const__ u32 __arch_bitrev32(u32 x)
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{
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unsigned long result;
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if (!riscv_has_extension_likely(RISCV_ISA_EXT_ZBKB))
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return generic___bitrev32(x);
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asm volatile(
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".option push\n"
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".option arch,+zbkb\n"
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"rev8 %0, %1\n"
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"brev8 %0, %0\n"
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".option pop"
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: "=r" (result) : "r" ((long)x)
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);
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return result >> (__riscv_xlen - 32);
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}
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static __always_inline __attribute_const__ u16 __arch_bitrev16(u16 x)
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{
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return __arch_bitrev32(x) >> 16;
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}
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static __always_inline __attribute_const__ u8 __arch_bitrev8(u8 x)
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{
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unsigned long result;
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if (!riscv_has_extension_likely(RISCV_ISA_EXT_ZBKB))
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return generic___bitrev8(x);
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asm volatile(
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".option push\n"
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".option arch,+zbkb\n"
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"brev8 %0, %1\n"
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".option pop"
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: "=r" (result) : "r" ((long)x)
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);
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return result;
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}
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#endif
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