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3dd31a370c
The assembly code of ip_fast_csum() triggers unaligned access warnings if the IP header isn't correctly aligned: Kernel: unaligned access to 0x173d22e76 in inet_gro_receive+0xbc/0x2e8 (iir 0x0e8810b6) Kernel: unaligned access to 0x173d22e7e in inet_gro_receive+0xc4/0x2e8 (iir 0x0e88109a) Kernel: unaligned access to 0x173d22e82 in inet_gro_receive+0xc8/0x2e8 (iir 0x0e90109d) Kernel: unaligned access to 0x173d22e7a in inet_gro_receive+0xd0/0x2e8 (iir 0x0e9810b8) Kernel: unaligned access to 0x173d22e86 in inet_gro_receive+0xdc/0x2e8 (iir 0x0e8810b8) We have the option to a) ignore the warnings, b) work around it by adding more code to check for alignment, or c) to switch to the generic implementation and rely on the compiler to optimize the code. Let's go with c), because a) isn't nice, and b) would effectively lead to an implementation which is basically equal to c). Signed-off-by: Helge Deller <deller@gmx.de> Cc: stable@vger.kernel.org # v7.0+
95 lines
2.5 KiB
C
95 lines
2.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _PARISC_CHECKSUM_H
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#define _PARISC_CHECKSUM_H
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#include <linux/in6.h>
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#define csum_tcpudp_nofold csum_tcpudp_nofold
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static inline __wsum csum_tcpudp_nofold(__be32 saddr, __be32 daddr,
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__u32 len, __u8 proto,
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__wsum sum)
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{
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__asm__(
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" add %1, %0, %0\n"
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" addc %2, %0, %0\n"
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" addc %3, %0, %0\n"
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" addc %%r0, %0, %0\n"
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: "=r" (sum)
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: "r" (daddr), "r"(saddr), "r"(proto+len), "0"(sum));
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return sum;
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}
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#include <asm-generic/checksum.h>
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#define _HAVE_ARCH_IPV6_CSUM
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static __inline__ __sum16 csum_ipv6_magic(const struct in6_addr *saddr,
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const struct in6_addr *daddr,
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__u32 len, __u8 proto,
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__wsum sum)
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{
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unsigned long t0, t1, t2, t3;
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len += proto; /* add 16-bit proto + len */
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__asm__ __volatile__ (
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#if BITS_PER_LONG > 32
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/*
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** We can execute two loads and two adds per cycle on PA 8000.
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** But add insn's get serialized waiting for the carry bit.
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** Try to keep 4 registers with "live" values ahead of the ALU.
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*/
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" depdi 0, 31, 32, %0\n"/* clear upper half of incoming checksum */
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" ldd,ma 8(%1), %4\n" /* get 1st saddr word */
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" ldd,ma 8(%2), %5\n" /* get 1st daddr word */
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" add %4, %0, %0\n"
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" ldd,ma 8(%1), %6\n" /* 2nd saddr */
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" ldd,ma 8(%2), %7\n" /* 2nd daddr */
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" add,dc %5, %0, %0\n"
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" add,dc %6, %0, %0\n"
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" add,dc %7, %0, %0\n"
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" add,dc %3, %0, %0\n" /* fold in proto+len | carry bit */
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" extrd,u %0, 31, 32, %4\n"/* copy upper half down */
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" depdi 0, 31, 32, %0\n"/* clear upper half */
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" add,dc %4, %0, %0\n" /* fold into 32-bits, plus carry */
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" addc 0, %0, %0\n" /* add final carry */
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#else
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/*
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** For PA 1.x, the insn order doesn't matter as much.
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** Insn stream is serialized on the carry bit here too.
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** result from the previous operation (eg r0 + x)
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*/
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" ldw,ma 4(%1), %4\n" /* get 1st saddr word */
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" ldw,ma 4(%2), %5\n" /* get 1st daddr word */
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" add %4, %0, %0\n"
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" ldw,ma 4(%1), %6\n" /* 2nd saddr */
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" addc %5, %0, %0\n"
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" ldw,ma 4(%2), %7\n" /* 2nd daddr */
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" addc %6, %0, %0\n"
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" ldw,ma 4(%1), %4\n" /* 3rd saddr */
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" addc %7, %0, %0\n"
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" ldw,ma 4(%2), %5\n" /* 3rd daddr */
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" addc %4, %0, %0\n"
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" ldw,ma 4(%1), %6\n" /* 4th saddr */
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" addc %5, %0, %0\n"
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" ldw,ma 4(%2), %7\n" /* 4th daddr */
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" addc %6, %0, %0\n"
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" addc %7, %0, %0\n"
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" addc %3, %0, %0\n" /* fold in proto+len */
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" addc 0, %0, %0\n" /* add carry */
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#endif
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: "=r" (sum), "=r" (saddr), "=r" (daddr), "=r" (len),
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"=r" (t0), "=r" (t1), "=r" (t2), "=r" (t3)
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: "0" (sum), "1" (saddr), "2" (daddr), "3" (len)
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: "memory");
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return csum_fold(sum);
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}
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#endif
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