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32ec465103
Loongson2ef reserves io range below 0x4000 (LOONGSON_PCI_IO_START) while ISA-mode only IDE controller on the south bridge still has a hard dependency on ISA IO ports. The reservation was done by lifting loongson_pci_io_resource.start onto 0x4000. Prior to commitae81aad5c2("MIPS: PCI: Use pci_enable_resources()"), the arch specific pcibios_enable_resources() did not check if the resources were claimed, which diverges from what PCI core checks, effectively hiding the fact that IDE IO resources were not properly within the resource tree. After starting to use pcibios_enable_resources() from PCI core, enabling IDE controller fails: pata_cs5536 0000:00:0e.2: BAR 0 [io 0x01f0-0x01f7]: not claimed; can't enable device pata_cs5536 0000:00:0e.2: probe with driver pata_cs5536 failed with error -22 MIPS PCI code already has support for enforcing lower bounds using PCIBIOS_MIN_IO in pcibios_align_resource() without altering the IO window start address itself. Make Loongson2ef PCI code use PCIBIOS_MIN_IO too. Fixes:ae81aad5c2("MIPS: PCI: Use pci_enable_resources()") Cc: stable@vger.kernel.org Tested-by: Beiyan Yun <root@infi.wang> Tested-by: Yao Zi <me@ziyao.cc> Signed-off-by: Rong Zhang <rongrong@oss.cipunited.com> Acked-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
92 lines
2.7 KiB
C
92 lines
2.7 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology
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* Author: Fuxin Zhang, zhangfx@lemote.com
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*/
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#include <linux/pci.h>
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#include <pci.h>
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#include <loongson.h>
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static struct resource loongson_pci_mem_resource = {
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.name = "pci memory space",
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.start = LOONGSON_PCI_MEM_START,
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.end = LOONGSON_PCI_MEM_END,
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.flags = IORESOURCE_MEM,
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};
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static struct resource loongson_pci_io_resource = {
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.name = "pci io space",
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.start = 0x00000000UL, /* See loongson2ef_pcibios_init(). */
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.end = IO_SPACE_LIMIT,
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.flags = IORESOURCE_IO,
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};
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static struct pci_controller loongson_pci_controller = {
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.pci_ops = &loongson_pci_ops,
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.io_resource = &loongson_pci_io_resource,
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.mem_resource = &loongson_pci_mem_resource,
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.mem_offset = 0x00000000UL,
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.io_offset = 0x00000000UL,
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};
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static void __init setup_pcimap(void)
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{
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/*
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* local to PCI mapping for CPU accessing PCI space
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* CPU address space [256M,448M] is window for accessing pci space
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* we set pcimap_lo[0,1,2] to map it to pci space[0M,64M], [320M,448M]
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*
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* pcimap: PCI_MAP2 PCI_Mem_Lo2 PCI_Mem_Lo1 PCI_Mem_Lo0
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* [<2G] [384M,448M] [320M,384M] [0M,64M]
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*/
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LOONGSON_PCIMAP = LOONGSON_PCIMAP_PCIMAP_2 |
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LOONGSON_PCIMAP_WIN(2, LOONGSON_PCILO2_BASE) |
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LOONGSON_PCIMAP_WIN(1, LOONGSON_PCILO1_BASE) |
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LOONGSON_PCIMAP_WIN(0, 0);
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/*
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* PCI-DMA to local mapping: [2G,2G+256M] -> [0M,256M]
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*/
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LOONGSON_PCIBASE0 = 0x80000000ul; /* base: 2G -> mmap: 0M */
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/* size: 256M, burst transmission, pre-fetch enable, 64bit */
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LOONGSON_PCI_HIT0_SEL_L = 0xc000000cul;
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LOONGSON_PCI_HIT0_SEL_H = 0xfffffffful;
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LOONGSON_PCI_HIT1_SEL_L = 0x00000006ul; /* set this BAR as invalid */
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LOONGSON_PCI_HIT1_SEL_H = 0x00000000ul;
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LOONGSON_PCI_HIT2_SEL_L = 0x00000006ul; /* set this BAR as invalid */
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LOONGSON_PCI_HIT2_SEL_H = 0x00000000ul;
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/* avoid deadlock of PCI reading/writing lock operation */
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LOONGSON_PCI_ISR4C = 0xd2000001ul;
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/* can not change gnt to break pci transfer when device's gnt not
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deassert for some broken device */
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LOONGSON_PXARB_CFG = 0x00fe0105ul;
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#ifdef CONFIG_CPU_SUPPORTS_ADDRWINCFG
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/*
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* set cpu addr window2 to map CPU address space to PCI address space
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*/
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LOONGSON_ADDRWIN_CPUTOPCI(ADDRWIN_WIN2, LOONGSON_CPU_MEM_SRC,
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LOONGSON_PCI_MEM_DST, MMAP_CPUTOPCI_SIZE);
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#endif
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}
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void __init loongson2ef_pcibios_init(void)
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{
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setup_pcimap();
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/*
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* ISA-mode only IDE controllers have a hard dependency on ISA IO ports.
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*
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* Claim them by setting PCI IO space to start at 0x00000000, and set
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* PCIBIOS_MIN_IO to prevent non-legacy PCI devices from touching
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* reserved regions.
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*/
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PCIBIOS_MIN_IO = LOONGSON_PCI_IO_START;
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loongson_pci_controller.io_map_base = mips_io_port_base;
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register_pci_controller(&loongson_pci_controller);
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}
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