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1dd3e8a8ee
The 8 and 16 bit read-modify-write atomic instructions amadd.{b/h} and
amswap.{b/h} were newly added in the latest LoongArch Reference Manual,
define the instruction format and check whether support via CPUCFG.
Furthermore, define the instruction format for DBAR which will be used
to support BPF load-acquire and store-release instructions.
This is preparation for later patches.
Acked-by: Hengqi Chen <hengqi.chen@gmail.com>
Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
133 lines
3.5 KiB
C
133 lines
3.5 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2020-2022 Loongson Technology Corporation Limited
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*/
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#include <linux/delay.h>
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/seq_file.h>
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#include <asm/bootinfo.h>
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#include <asm/cpu.h>
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#include <asm/cpu-features.h>
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#include <asm/idle.h>
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#include <asm/processor.h>
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#include <asm/time.h>
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static int show_cpuinfo(struct seq_file *m, void *v)
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{
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unsigned long n = (unsigned long) v - 1;
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unsigned int isa = cpu_data[n].isa_level;
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unsigned int prid = cpu_data[n].processor_id;
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unsigned int version = cpu_data[n].processor_id & 0xff;
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unsigned int fp_version = cpu_data[n].fpu_vers;
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u64 freq = cpu_clock_freq, bogomips = lpj_fine * cpu_clock_freq;
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#ifdef CONFIG_SMP
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if (!cpu_online(n))
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return 0;
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#endif
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do_div(freq, 10000);
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do_div(bogomips, const_clock_freq * (5000/HZ));
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/*
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* For the first processor also print the system type
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*/
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if (n == 0)
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seq_printf(m, "system type\t\t: %s\n\n", get_system_type());
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seq_printf(m, "processor\t\t: %ld\n", n);
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seq_printf(m, "package\t\t\t: %d\n", cpu_data[n].package);
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seq_printf(m, "core\t\t\t: %d\n", cpu_data[n].core);
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seq_printf(m, "global_id\t\t: %d\n", cpu_data[n].global_id);
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seq_printf(m, "CPU Family\t\t: %s\n", __cpu_family[n]);
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seq_printf(m, "Model Name\t\t: %s\n", __cpu_full_name[n]);
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seq_printf(m, "PRID\t\t\t: %s (%08x)\n", id_to_core_name(prid), prid);
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seq_printf(m, "CPU Revision\t\t: 0x%02x\n", version);
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seq_printf(m, "FPU Revision\t\t: 0x%02x\n", fp_version);
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seq_printf(m, "CPU MHz\t\t\t: %u.%02u\n", (u32)freq / 100, (u32)freq % 100);
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seq_printf(m, "BogoMIPS\t\t: %u.%02u\n", (u32)bogomips / 100, (u32)bogomips % 100);
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seq_printf(m, "TLB Entries\t\t: %d\n", cpu_data[n].tlbsize);
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seq_printf(m, "Address Sizes\t\t: %d bits physical, %d bits virtual\n",
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cpu_pabits + 1, cpu_vabits + 1);
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seq_puts(m, "ISA\t\t\t:");
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if (isa & LOONGARCH_CPU_ISA_LA32R)
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seq_puts(m, " loongarch32r");
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if (isa & LOONGARCH_CPU_ISA_LA32S)
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seq_puts(m, " loongarch32s");
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if (isa & LOONGARCH_CPU_ISA_LA64)
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seq_puts(m, " loongarch64");
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seq_puts(m, "\n");
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seq_puts(m, "Features\t\t:");
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if (cpu_has_cpucfg)
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seq_puts(m, " cpucfg");
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if (cpu_has_lam)
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seq_puts(m, " lam");
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if (cpu_has_lam_bh)
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seq_puts(m, " lam_bh");
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if (cpu_has_scq)
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seq_puts(m, " scq");
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if (cpu_has_ual)
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seq_puts(m, " ual");
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if (cpu_has_fpu)
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seq_puts(m, " fpu");
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if (cpu_has_lsx)
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seq_puts(m, " lsx");
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if (cpu_has_lasx)
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seq_puts(m, " lasx");
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if (cpu_has_crc32)
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seq_puts(m, " crc32");
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if (cpu_has_complex)
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seq_puts(m, " complex");
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if (cpu_has_crypto)
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seq_puts(m, " crypto");
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if (cpu_has_ptw)
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seq_puts(m, " ptw");
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if (cpu_has_lspw)
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seq_puts(m, " lspw");
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if (cpu_has_lvz)
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seq_puts(m, " lvz");
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if (cpu_has_lbt_x86)
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seq_puts(m, " lbt_x86");
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if (cpu_has_lbt_arm)
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seq_puts(m, " lbt_arm");
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if (cpu_has_lbt_mips)
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seq_puts(m, " lbt_mips");
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seq_puts(m, "\n");
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seq_printf(m, "Hardware Watchpoint\t: %s", str_yes_no(cpu_has_watch));
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if (cpu_has_watch) {
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seq_printf(m, ", iwatch count: %d, dwatch count: %d",
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cpu_data[n].watch_ireg_count, cpu_data[n].watch_dreg_count);
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}
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seq_puts(m, "\n\n");
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return 0;
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}
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static void *c_start(struct seq_file *m, loff_t *pos)
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{
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unsigned long i = *pos;
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return i < nr_cpu_ids ? (void *)(i + 1) : NULL;
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}
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static void *c_next(struct seq_file *m, void *v, loff_t *pos)
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{
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++*pos;
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return c_start(m, pos);
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}
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static void c_stop(struct seq_file *m, void *v)
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{
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}
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const struct seq_operations cpuinfo_op = {
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.start = c_start,
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.next = c_next,
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.stop = c_stop,
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.show = show_cpuinfo,
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};
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