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Loongson 7A PCH chips all contain a LPC controller, which is used in some devices to connect legacy ISA devices (e.g. 8259 PS/2 controller). The LPC irqchip driver will register LPC interrupts at the fixed range 0~15, and the PCH PIC irqchip driver uses dynamic allocation. However the LPC interrupt numbers are currently not exempted from dynamic allocation. The current setup work by accident because the LPC interrupt controller is the first consumer of PIC interrupt controller, and the PIC interrupt number is allocated after LPC interrupts are registered. Such setup is fragile and will stop to work when the LPC irqchip driver is reworked. Override arch_dynirq_lower_bound() to reserve LPC interrupts from dynamic allocation, to prevent interrupt number collision and allow rework of the LPC irqchip driver. Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Reviewed-by: Huacai Chen <chenhuacai@loongson.cn> Link: https://patch.msgid.link/20260321092032.3502701-3-zhengxingda@iscas.ac.cn
133 lines
3.1 KiB
C
133 lines
3.1 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2020-2022 Loongson Technology Corporation Limited
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*/
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#include <linux/kernel.h>
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#include <linux/acpi.h>
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#include <linux/atomic.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/irqchip.h>
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#include <linux/kernel_stat.h>
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#include <linux/proc_fs.h>
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#include <linux/minmax.h>
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#include <linux/mm.h>
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#include <linux/sched.h>
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#include <linux/seq_file.h>
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#include <linux/kallsyms.h>
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#include <linux/uaccess.h>
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#include <asm/irq.h>
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#include <asm/loongson.h>
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#include <asm/setup.h>
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DEFINE_PER_CPU(unsigned long, irq_stack);
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DEFINE_PER_CPU_SHARED_ALIGNED(irq_cpustat_t, irq_stat);
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EXPORT_PER_CPU_SYMBOL(irq_stat);
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struct acpi_vector_group pch_group[MAX_IO_PICS];
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struct acpi_vector_group msi_group[MAX_IO_PICS];
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/*
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* 'what should we do if we get a hw irq event on an illegal vector'.
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* each architecture has to answer this themselves.
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*/
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void ack_bad_irq(unsigned int irq)
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{
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pr_warn("Unexpected IRQ # %d\n", irq);
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}
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atomic_t irq_err_count;
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asmlinkage void spurious_interrupt(void)
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{
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atomic_inc(&irq_err_count);
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}
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int arch_show_interrupts(struct seq_file *p, int prec)
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{
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#ifdef CONFIG_SMP
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show_ipi_list(p, prec);
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#endif
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seq_printf(p, "%*s: %10u\n", prec, "ERR", atomic_read(&irq_err_count));
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return 0;
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}
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static int __init early_pci_mcfg_parse(struct acpi_table_header *header)
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{
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struct acpi_table_mcfg *mcfg;
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struct acpi_mcfg_allocation *mptr;
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int i, n;
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if (header->length < sizeof(struct acpi_table_mcfg))
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return -EINVAL;
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n = (header->length - sizeof(struct acpi_table_mcfg)) /
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sizeof(struct acpi_mcfg_allocation);
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mcfg = (struct acpi_table_mcfg *)header;
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mptr = (struct acpi_mcfg_allocation *) &mcfg[1];
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for (i = 0; i < n; i++, mptr++) {
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msi_group[i].pci_segment = mptr->pci_segment;
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pch_group[i].node = msi_group[i].node = (mptr->address >> 44) & 0xf;
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}
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return 0;
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}
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static void __init init_vec_parent_group(void)
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{
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int i;
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for (i = 0; i < MAX_IO_PICS; i++) {
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msi_group[i].pci_segment = -1;
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msi_group[i].node = -1;
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pch_group[i].node = -1;
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}
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acpi_table_parse(ACPI_SIG_MCFG, early_pci_mcfg_parse);
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}
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int __init arch_probe_nr_irqs(void)
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{
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int nr_io_pics = bitmap_weight(loongson_sysconf.cores_io_master, NR_CPUS);
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if (!cpu_has_avecint)
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irq_set_nr_irqs(64 + NR_VECTORS * nr_io_pics);
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else
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irq_set_nr_irqs(64 + NR_VECTORS * (nr_cpu_ids + nr_io_pics));
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return NR_IRQS_LEGACY;
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}
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unsigned int arch_dynirq_lower_bound(unsigned int from)
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{
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return MAX(from, NR_IRQS_LEGACY);
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}
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void __init init_IRQ(void)
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{
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int i;
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unsigned int order = get_order(IRQ_STACK_SIZE);
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struct page *page;
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clear_csr_ecfg(ECFG0_IM);
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clear_csr_estat(ESTATF_IP);
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init_vec_parent_group();
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irqchip_init();
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#ifdef CONFIG_SMP
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mp_ops.init_ipi();
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#endif
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for_each_possible_cpu(i) {
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page = alloc_pages_node(cpu_to_node(i), GFP_KERNEL, order);
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per_cpu(irq_stack, i) = (unsigned long)page_address(page);
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pr_debug("CPU%d IRQ stack at 0x%lx - 0x%lx\n", i,
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per_cpu(irq_stack, i), per_cpu(irq_stack, i) + IRQ_STACK_SIZE);
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}
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set_csr_ecfg(ECFGF_SIP0 | ECFGF_IP0 | ECFGF_IP1 | ECFGF_IP2 | ECFGF_IPI | ECFGF_PMC);
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}
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