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0baba94a97
C1-Pro acknowledges DVMSync messages before completing the SME/CME memory accesses. Work around this by issuing an IPI to the affected CPUs if they are running in EL0 with SME enabled. Note that we avoid the local DSB in the IPI handler as the kernel runs with SCTLR_EL1.IESB=1. This is sufficient to complete SME memory accesses at EL0 on taking an exception to EL1. On the return to user path, no barrier is necessary either. See the comment in sme_set_active() and the more detailed explanation in the link below. To avoid a potential IPI flood from malicious applications (e.g. madvise(MADV_PAGEOUT) in a tight loop), track where a process is active via mm_cpumask() and only interrupt those CPUs. Link: https://lore.kernel.org/r/ablEXwhfKyJW1i7l@J2N7QTR9R3 Cc: Will Deacon <will@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: James Morse <james.morse@arm.com> Cc: Mark Brown <broonie@kernel.org> Reviewed-by: Will Deacon <will@kernel.org> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
19 lines
452 B
C
19 lines
452 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ARCH_ARM64_TLBBATCH_H
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#define _ARCH_ARM64_TLBBATCH_H
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#include <linux/cpumask.h>
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struct arch_tlbflush_unmap_batch {
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#ifdef CONFIG_ARM64_ERRATUM_4193714
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/*
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* Track CPUs that need SME DVMSync on completion of this batch.
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* Otherwise, the arm64 HW can do tlb shootdown, so we don't need to
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* record cpumask for sending IPI
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*/
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cpumask_var_t cpumask;
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#endif
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};
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#endif /* _ARCH_ARM64_TLBBATCH_H */
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