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i.MX952 is designed for AI-powered sensor fusion and vision sensing applications, it features 4 Corte-A55, 1 Cortex-M33, 1 Cortex-M7 and NXP eIQ NPU and advanced graphics, video and advanced security with edgelock. Product info could be found at: https://www.nxp.com/products/i.MX-952 The basic device tree includes: - clock, pin, power header files - device nodes: CPU[0-3], SCMI firmware, Interrupt Controller, Sys counter, eDMA, MU, SPI, UART, I2C, USB and etc Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
216 lines
6.7 KiB
C
216 lines
6.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
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/*
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* Copyright 2025 NXP
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*/
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#ifndef __CLOCK_IMX952_H__
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#define __CLOCK_IMX952_H__
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/* Clock Source */
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#define IMX952_CLK_EXT 0
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#define IMX952_CLK_OSC32K 1
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#define IMX952_CLK_OSC24M 2
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#define IMX952_CLK_FRO 3
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#define IMX952_CLK_SYSPLL1_VCO 4
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#define IMX952_CLK_SYSPLL1_PFD0_UNGATED 5
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#define IMX952_CLK_SYSPLL1_PFD0 6
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#define IMX952_CLK_SYSPLL1_PFD0_DIV2 7
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#define IMX952_CLK_SYSPLL1_PFD1_UNGATED 8
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#define IMX952_CLK_SYSPLL1_PFD1 9
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#define IMX952_CLK_SYSPLL1_PFD1_DIV2 10
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#define IMX952_CLK_SYSPLL1_PFD2_UNGATED 11
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#define IMX952_CLK_SYSPLL1_PFD2 12
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#define IMX952_CLK_SYSPLL1_PFD2_DIV2 13
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#define IMX952_CLK_AUDIOPLL1_VCO 14
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#define IMX952_CLK_AUDIOPLL1 15
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#define IMX952_CLK_AUDIOPLL2_VCO 16
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#define IMX952_CLK_AUDIOPLL2 17
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#define IMX952_CLK_VIDEOPLL1_VCO 18
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#define IMX952_CLK_VIDEOPLL1 19
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#define IMX952_CLK_SRC_RESERVED20 20
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#define IMX952_CLK_SYSPLL1_PFD3_UNGATED 21
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#define IMX952_CLK_SYSPLL1_PFD3 22
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#define IMX952_CLK_SYSPLL1_PFD3_DIV2 23
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#define IMX952_CLK_ARMPLL_VCO 24
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#define IMX952_CLK_ARMPLL_PFD0_UNGATED 25
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#define IMX952_CLK_ARMPLL_PFD0 26
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#define IMX952_CLK_ARMPLL_PFD1_UNGATED 27
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#define IMX952_CLK_ARMPLL_PFD1 28
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#define IMX952_CLK_ARMPLL_PFD2_UNGATED 29
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#define IMX952_CLK_ARMPLL_PFD2 30
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#define IMX952_CLK_ARMPLL_PFD3_UNGATED 31
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#define IMX952_CLK_ARMPLL_PFD3 32
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#define IMX952_CLK_DRAMPLL_VCO 33
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#define IMX952_CLK_DRAMPLL 34
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#define IMX952_CLK_HSIOPLL_VCO 35
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#define IMX952_CLK_HSIOPLL 36
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#define IMX952_CLK_LDBPLL_VCO 37
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#define IMX952_CLK_LDBPLL 38
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#define IMX952_CLK_EXT1 39
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#define IMX952_CLK_EXT2 40
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/* Clock ROOT */
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#define IMX952_CLK_ADC 41
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#define IMX952_CLK_RESERVED1 42
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#define IMX952_CLK_BUSAON 43
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#define IMX952_CLK_CAN1 44
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#define IMX952_CLK_RESERVED4 45
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#define IMX952_CLK_I3C1SLOW 46
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#define IMX952_CLK_LPI2C1 47
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#define IMX952_CLK_LPI2C2 48
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#define IMX952_CLK_LPSPI1 49
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#define IMX952_CLK_LPSPI2 50
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#define IMX952_CLK_LPTMR1 51
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#define IMX952_CLK_LPUART1 52
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#define IMX952_CLK_LPUART2 53
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#define IMX952_CLK_M33 54
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#define IMX952_CLK_M33SYSTICK 55
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#define IMX952_CLK_RESERVED15 56
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#define IMX952_CLK_PDM 57
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#define IMX952_CLK_SAI1 58
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#define IMX952_CLK_RESERVED18 59
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#define IMX952_CLK_TPM2 60
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#define IMX952_CLK_RESERVED20 61
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#define IMX952_CLK_CAMAPB 62
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#define IMX952_CLK_CAMAXI 63
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#define IMX952_CLK_CAMCM0 64
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#define IMX952_CLK_CAMISI 65
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#define IMX952_CLK_CAMPHYCFG 66
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#define IMX952_CLK_MIPIPHYPLLBYPASS 67
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#define IMX952_CLK_RESERVED27 68
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#define IMX952_CLK_MIPITESTBYTE 69
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#define IMX952_CLK_A55 70
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#define IMX952_CLK_A55MTRBUS 71
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#define IMX952_CLK_A55PERIPH 72
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#define IMX952_CLK_DRAMALT 73
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#define IMX952_CLK_DRAMAPB 74
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#define IMX952_CLK_DISPAPB 75
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#define IMX952_CLK_DISPAXI 76
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#define IMX952_CLK_DISPLPSPI 77
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#define IMX952_CLK_DISPOCRAM 78
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#define IMX952_CLK_DISPPHYCFG 79
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#define IMX952_CLK_DISP1PIX 80
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#define IMX952_CLK_DISPCDPHYAPB 81
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#define IMX952_CLK_RESERVED41 82
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#define IMX952_CLK_GPUAPB 83
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#define IMX952_CLK_GPU 84
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#define IMX952_CLK_HSIOACSCAN480M 85
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#define IMX952_CLK_HSIOACSCAN80M 86
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#define IMX952_CLK_HSIO 87
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#define IMX952_CLK_HSIOPCIEAUX 88
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#define IMX952_CLK_HSIOPCIETEST160M 89
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#define IMX952_CLK_HSIOPCIETEST400M 90
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#define IMX952_CLK_HSIOPCIETEST500M 91
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#define IMX952_CLK_HSIOUSBTEST50M 92
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#define IMX952_CLK_HSIOUSBTEST60M 93
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#define IMX952_CLK_BUSM7 94
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#define IMX952_CLK_M7 95
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#define IMX952_CLK_M7SYSTICK 96
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#define IMX952_CLK_BUSNETCMIX 97
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#define IMX952_CLK_ENET 98
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#define IMX952_CLK_ENETPHYTEST200M 99
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#define IMX952_CLK_ENETPHYTEST500M 100
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#define IMX952_CLK_ENETPHYTEST667M 101
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#define IMX952_CLK_ENETREF 102
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#define IMX952_CLK_ENETTIMER1 103
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#define IMX952_CLK_RESERVED63 104
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#define IMX952_CLK_SAI2 105
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#define IMX952_CLK_NOCAPB 106
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#define IMX952_CLK_NOC 107
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#define IMX952_CLK_NPUAPB 108
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#define IMX952_CLK_NPU 109
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#define IMX952_CLK_CCMCKO1 110
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#define IMX952_CLK_CCMCKO2 111
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#define IMX952_CLK_CCMCKO3 112
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#define IMX952_CLK_CCMCKO4 113
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#define IMX952_CLK_VPUAPB 114
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#define IMX952_CLK_VPU 115
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#define IMX952_CLK_RESERVED75 116
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#define IMX952_CLK_RESERVED76 117
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#define IMX952_CLK_AUDIOXCVR 118
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#define IMX952_CLK_BUSWAKEUP 119
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#define IMX952_CLK_CAN2 120
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#define IMX952_CLK_CAN3 121
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#define IMX952_CLK_CAN4 122
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#define IMX952_CLK_CAN5 123
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#define IMX952_CLK_FLEXIO1 124
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#define IMX952_CLK_FLEXIO2 125
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#define IMX952_CLK_XSPI1 126
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#define IMX952_CLK_RESERVED86 127
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#define IMX952_CLK_I3C2SLOW 128
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#define IMX952_CLK_LPI2C3 129
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#define IMX952_CLK_LPI2C4 130
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#define IMX952_CLK_LPI2C5 131
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#define IMX952_CLK_LPI2C6 132
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#define IMX952_CLK_LPI2C7 133
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#define IMX952_CLK_LPI2C8 134
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#define IMX952_CLK_LPSPI3 135
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#define IMX952_CLK_LPSPI4 136
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#define IMX952_CLK_LPSPI5 137
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#define IMX952_CLK_LPSPI6 138
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#define IMX952_CLK_LPSPI7 139
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#define IMX952_CLK_LPSPI8 140
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#define IMX952_CLK_LPTMR2 141
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#define IMX952_CLK_LPUART3 142
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#define IMX952_CLK_LPUART4 143
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#define IMX952_CLK_LPUART5 144
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#define IMX952_CLK_LPUART6 145
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#define IMX952_CLK_LPUART7 146
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#define IMX952_CLK_LPUART8 147
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#define IMX952_CLK_SAI3 148
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#define IMX952_CLK_SAI4 149
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#define IMX952_CLK_SAI5 150
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#define IMX952_CLK_SPDIF 151
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#define IMX952_CLK_SWOTRACE 152
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#define IMX952_CLK_TPM4 153
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#define IMX952_CLK_TPM5 154
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#define IMX952_CLK_TPM6 155
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#define IMX952_CLK_MIPIPHYDFT400 156
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#define IMX952_CLK_MIPIPHYDFT540 157
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#define IMX952_CLK_USDHC1 158
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#define IMX952_CLK_USDHC2 159
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#define IMX952_CLK_USDHC3 160
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#define IMX952_CLK_V2XPK 161
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#define IMX952_CLK_WAKEUPAXI 162
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#define IMX952_CLK_XSPISLVROOT 163
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#define IMX952_CLK_AUDMIX1 164
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#define IMX952_CLK_ASRC1 165
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#define IMX952_CLK_ASRC2 166
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#define IMX952_CLK_GPT1 167
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#define IMX952_CLK_GPT2 168
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#define IMX952_CLK_GPT3 169
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#define IMX952_CLK_GPT4 170
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/* Clock GPR SEL */
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#define IMX952_CLK_GPR_SEL_EXT 171
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#define IMX952_CLK_GPR_SEL_A55C0 172
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#define IMX952_CLK_GPR_SEL_A55C1 173
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#define IMX952_CLK_GPR_SEL_A55C2 174
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#define IMX952_CLK_GPR_SEL_A55C3 175
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#define IMX952_CLK_GPR_SEL_A55P 176
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#define IMX952_CLK_GPR_SEL_DRAM 177
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#define IMX952_CLK_GPR_SEL_TEMPSENSE 178
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/* Clock CGC */
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#define IMX952_CLK_CGC_NPU 179
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#define IMX952_CLK_CGC_GPU 180
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#define IMX952_CLK_CGC_CAMISI 181
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#define IMX952_CLK_CGC_CAMISP 182
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#define IMX952_CLK_CGC_CAMCSI0 183
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#define IMX952_CLK_CGC_CAMCSI1 184
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#define IMX952_CLK_CGC_CAMOCRAM 185
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#define IMX952_CLK_CGC_HSIOUSB 186
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#define IMX952_CLK_CGC_HSIOPCIE 187
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#define IMX952_CLK_CGC_DISPOCRAM 188
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#define IMX952_CLK_CGC_DISPSEERIS 189
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#define IMX952_CLK_CGC_DISPDSI 190
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#define IMX952_CLK_CGC_NOCGIC 191
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#define IMX952_CLK_CGC_NOCOCRAM 192
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#define IMX952_CLK_CGC_NETC 193
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#define IMX952_CLK_CGC_VPUENC 194
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#define IMX952_CLK_CGC_VPUJPEGENC 195
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#define IMX952_CLK_CGC_VPUJPEGDEC 196
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#define IMX952_CLK_CGC_VPUDEC 197
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#endif
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