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Since describing the PCIe PERST# property under Host Bridge node is now deprecated, it is recommended to add it to the Root Port node, so creating the root port node and pave the path to add the reset-gpios and so on properties in root port later. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
300 lines
7.6 KiB
Plaintext
300 lines
7.6 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright 2025 NXP
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*/
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#include "imx94.dtsi"
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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idle-states {
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entry-method = "psci";
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cpu_pd_wait: cpu-pd-wait {
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compatible = "arm,idle-state";
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arm,psci-suspend-param = <0x0010033>;
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local-timer-stop;
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entry-latency-us = <1000>;
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exit-latency-us = <700>;
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min-residency-us = <2700>;
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wakeup-latency-us = <1500>;
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};
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};
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cpu0: cpu@0 {
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compatible = "arm,cortex-a55";
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device_type = "cpu";
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reg = <0x0>;
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enable-method = "psci";
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#cooling-cells = <2>;
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cpu-idle-states = <&cpu_pd_wait>;
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power-domains = <&scmi_perf IMX94_PERF_A55>;
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power-domain-names = "perf";
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i-cache-size = <32768>;
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i-cache-line-size = <64>;
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i-cache-sets = <128>;
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d-cache-size = <32768>;
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d-cache-line-size = <64>;
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d-cache-sets = <128>;
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next-level-cache = <&l2_cache_l0>;
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};
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cpu1: cpu@100 {
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compatible = "arm,cortex-a55";
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device_type = "cpu";
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reg = <0x100>;
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enable-method = "psci";
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#cooling-cells = <2>;
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cpu-idle-states = <&cpu_pd_wait>;
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power-domains = <&scmi_perf IMX94_PERF_A55>;
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power-domain-names = "perf";
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i-cache-size = <32768>;
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i-cache-line-size = <64>;
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i-cache-sets = <128>;
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d-cache-size = <32768>;
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d-cache-line-size = <64>;
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d-cache-sets = <128>;
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next-level-cache = <&l2_cache_l1>;
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};
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cpu2: cpu@200 {
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compatible = "arm,cortex-a55";
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device_type = "cpu";
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reg = <0x200>;
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enable-method = "psci";
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#cooling-cells = <2>;
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cpu-idle-states = <&cpu_pd_wait>;
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power-domains = <&scmi_perf IMX94_PERF_A55>;
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power-domain-names = "perf";
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i-cache-size = <32768>;
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i-cache-line-size = <64>;
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i-cache-sets = <128>;
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d-cache-size = <32768>;
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d-cache-line-size = <64>;
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d-cache-sets = <128>;
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next-level-cache = <&l2_cache_l2>;
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};
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cpu3: cpu@300 {
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compatible = "arm,cortex-a55";
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device_type = "cpu";
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reg = <0x300>;
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enable-method = "psci";
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#cooling-cells = <2>;
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cpu-idle-states = <&cpu_pd_wait>;
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power-domains = <&scmi_perf IMX94_PERF_A55>;
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power-domain-names = "perf";
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i-cache-size = <32768>;
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i-cache-line-size = <64>;
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i-cache-sets = <128>;
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d-cache-size = <32768>;
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d-cache-line-size = <64>;
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d-cache-sets = <128>;
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next-level-cache = <&l2_cache_l3>;
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};
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l2_cache_l0: l2-cache-l0 {
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compatible = "cache";
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cache-size = <65536>;
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cache-line-size = <64>;
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cache-sets = <256>;
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&l3_cache>;
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};
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l2_cache_l1: l2-cache-l1 {
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compatible = "cache";
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cache-size = <65536>;
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cache-line-size = <64>;
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cache-sets = <256>;
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&l3_cache>;
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};
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l2_cache_l2: l2-cache-l2 {
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compatible = "cache";
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cache-size = <65536>;
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cache-line-size = <64>;
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cache-sets = <256>;
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&l3_cache>;
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};
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l2_cache_l3: l2-cache-l3 {
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compatible = "cache";
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cache-size = <65536>;
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cache-line-size = <64>;
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cache-sets = <256>;
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&l3_cache>;
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};
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l3_cache: l3-cache {
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compatible = "cache";
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cache-size = <1048576>;
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cache-line-size = <64>;
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cache-sets = <1024>;
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cache-level = <3>;
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cache-unified;
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};
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};
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thermal_zones: thermal-zones {
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a55-thermal {
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polling-delay-passive = <250>;
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polling-delay = <2000>;
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thermal-sensors = <&scmi_sensor 1>;
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trips {
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cpu_alert0: trip0 {
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temperature = <105000>;
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hysteresis = <2000>;
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type = "passive";
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};
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cpu_crit0: trip1 {
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temperature = <125000>;
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hysteresis = <2000>;
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type = "critical";
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};
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};
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cooling-maps {
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map0 {
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trip = <&cpu_alert0>;
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cooling-device =
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<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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};
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};
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};
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ana-thermal {
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polling-delay-passive = <250>;
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polling-delay = <2000>;
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thermal-sensors = <&scmi_sensor 0>;
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trips {
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ana_alert: trip0 {
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temperature = <105000>;
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hysteresis = <2000>;
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type = "passive";
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};
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ana_crit0: trip1 {
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temperature = <125000>;
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hysteresis = <2000>;
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type = "critical";
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};
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};
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cooling-maps {
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map0 {
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trip = <&ana_alert>;
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cooling-device =
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<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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};
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};
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};
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};
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soc {
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pcie1: pcie@4c380000 {
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compatible = "fsl,imx943-pcie", "fsl,imx95-pcie";
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reg = <0 0x4c380000 0 0x10000>,
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<8 0x80100000 0 0xfe00000>,
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<0 0x4c3e0000 0 0x10000>,
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<0 0x4c3c0000 0 0x4000>;
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reg-names = "dbi", "config", "atu", "app";
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ranges = <0x43000000 0xa 0x00000000 0xa 0x00000000 0x0 0xe0000000>,
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<0x82000000 0x0 0xe0000000 0xa 0xe0000000 0x0 0x10000000>,
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<0x81000000 0x0 0x00000000 0xa 0xf0000000 0x0 0x00100000>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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linux,pci-domain = <3>;
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msi-map = <0x0 &its 0x98 0x1>,
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<0x100 &its 0x99 0x7>;
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msi-map-mask = <0x1ff>;
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bus-range = <0x00 0xff>;
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num-lanes = <1>;
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num-viewport = <8>;
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interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "msi", "dma";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 2 &gic 0 0 GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 3 &gic 0 0 GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 4 &gic 0 0 GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&scmi_clk IMX94_CLK_HSIO>,
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<&scmi_clk IMX94_CLK_HSIOPLL>,
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<&scmi_clk IMX94_CLK_HSIOPLL_VCO>,
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<&scmi_clk IMX94_CLK_HSIOPCIEAUX>,
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<&hsio_blk_ctl 0>;
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clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref";
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assigned-clocks = <&scmi_clk IMX94_CLK_HSIOPLL_VCO>,
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<&scmi_clk IMX94_CLK_HSIOPLL>,
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<&scmi_clk IMX94_CLK_HSIOPCIEAUX>;
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assigned-clock-rates = <3600000000>, <100000000>, <10000000>;
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assigned-clock-parents = <0>, <0>,
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<&scmi_clk IMX94_CLK_SYSPLL1_PFD1_DIV2>;
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power-domains = <&scmi_devpd IMX94_PD_HSIO_TOP>;
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fsl,max-link-speed = <3>;
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status = "disabled";
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pcie1_port0: pcie@0 {
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compatible = "pciclass,0604";
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device_type = "pci";
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reg = <0x0 0x0 0x0 0x0 0x0>;
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bus-range = <0x01 0xff>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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};
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};
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pcie1_ep: pcie-ep@4c380000 {
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compatible = "fsl,imx943-pcie-ep", "fsl,imx95-pcie-ep";
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reg = <0 0x4c380000 0 0x10000>,
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<0 0x4c3e0000 0 0x1000>,
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<0 0x4c3a0000 0 0x1000>,
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<0 0x4c3c0000 0 0x4000>,
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<0 0x4c3f0000 0 0x10000>,
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<0xa 0 1 0>;
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reg-names = "dbi", "atu", "dbi2", "app", "dma", "addr_space";
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num-lanes = <1>;
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interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "dma";
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clocks = <&scmi_clk IMX94_CLK_HSIO>,
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<&scmi_clk IMX94_CLK_HSIOPLL>,
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<&scmi_clk IMX94_CLK_HSIOPLL_VCO>,
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<&scmi_clk IMX94_CLK_HSIOPCIEAUX>;
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clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";
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assigned-clocks = <&scmi_clk IMX94_CLK_HSIOPLL_VCO>,
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<&scmi_clk IMX94_CLK_HSIOPLL>,
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<&scmi_clk IMX94_CLK_HSIOPCIEAUX>;
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assigned-clock-rates = <3600000000>, <100000000>, <10000000>;
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assigned-clock-parents = <0>, <0>,
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<&scmi_clk IMX94_CLK_SYSPLL1_PFD1_DIV2>;
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msi-map = <0x0 &its 0x98 0x1>;
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power-domains = <&scmi_devpd IMX94_PD_HSIO_TOP>;
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status = "disabled";
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};
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};
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};
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