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64b00da69e
Add Cadence GPIO controller nodes for Sky1 FCH(S0) and S5 domains in sky1.dtsi, and enable those controllers on sky1-orion-o6. Signed-off-by: Zichar Zhang <zichar.zhang@cixtech.com> Link: https://lore.kernel.org/r/20260312080826.3470205-2-zichar.zhang@cixtech.com Signed-off-by: Peter Chen <peter.chen@cixtech.com>
739 lines
19 KiB
Plaintext
739 lines
19 KiB
Plaintext
// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright 2025 Cix Technology Group Co., Ltd.
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*
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/cix,sky1.h>
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#include "sky1-power.h"
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/ {
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,cortex-a520";
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enable-method = "psci";
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reg = <0x0 0x0>;
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device_type = "cpu";
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capacity-dmips-mhz = <403>;
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};
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cpu1: cpu@100 {
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compatible = "arm,cortex-a520";
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enable-method = "psci";
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reg = <0x0 0x100>;
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device_type = "cpu";
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capacity-dmips-mhz = <403>;
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};
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cpu2: cpu@200 {
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compatible = "arm,cortex-a520";
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enable-method = "psci";
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reg = <0x0 0x200>;
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device_type = "cpu";
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capacity-dmips-mhz = <403>;
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};
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cpu3: cpu@300 {
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compatible = "arm,cortex-a520";
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enable-method = "psci";
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reg = <0x0 0x300>;
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device_type = "cpu";
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capacity-dmips-mhz = <403>;
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};
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cpu4: cpu@400 {
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compatible = "arm,cortex-a720";
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enable-method = "psci";
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reg = <0x0 0x400>;
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device_type = "cpu";
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capacity-dmips-mhz = <1024>;
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};
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cpu5: cpu@500 {
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compatible = "arm,cortex-a720";
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enable-method = "psci";
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reg = <0x0 0x500>;
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device_type = "cpu";
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capacity-dmips-mhz = <1024>;
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};
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cpu6: cpu@600 {
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compatible = "arm,cortex-a720";
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enable-method = "psci";
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reg = <0x0 0x600>;
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device_type = "cpu";
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capacity-dmips-mhz = <1024>;
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};
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cpu7: cpu@700 {
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compatible = "arm,cortex-a720";
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enable-method = "psci";
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reg = <0x0 0x700>;
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device_type = "cpu";
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capacity-dmips-mhz = <1024>;
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};
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cpu8: cpu@800 {
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compatible = "arm,cortex-a720";
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enable-method = "psci";
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reg = <0x0 0x800>;
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device_type = "cpu";
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capacity-dmips-mhz = <1024>;
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};
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cpu9: cpu@900 {
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compatible = "arm,cortex-a720";
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enable-method = "psci";
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reg = <0x0 0x900>;
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device_type = "cpu";
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capacity-dmips-mhz = <1024>;
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};
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cpu10: cpu@a00 {
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compatible = "arm,cortex-a720";
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enable-method = "psci";
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reg = <0x0 0xa00>;
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device_type = "cpu";
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capacity-dmips-mhz = <1024>;
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};
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cpu11: cpu@b00 {
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compatible = "arm,cortex-a720";
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enable-method = "psci";
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reg = <0x0 0xb00>;
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device_type = "cpu";
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capacity-dmips-mhz = <1024>;
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};
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&cpu0>;
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};
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core1 {
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cpu = <&cpu1>;
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};
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core2 {
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cpu = <&cpu2>;
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};
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core3 {
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cpu = <&cpu3>;
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};
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core4 {
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cpu = <&cpu4>;
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};
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core5 {
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cpu = <&cpu5>;
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};
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core6 {
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cpu = <&cpu6>;
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};
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core7 {
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cpu = <&cpu7>;
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};
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core8 {
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cpu = <&cpu8>;
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};
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core9 {
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cpu = <&cpu9>;
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};
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core10 {
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cpu = <&cpu10>;
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};
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core11 {
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cpu = <&cpu11>;
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};
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};
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};
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};
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firmware {
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ap_to_pm_scmi: scmi {
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compatible = "arm,scmi";
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mbox-names = "tx", "rx";
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mboxes = <&mbox_ap2pm 8>, <&mbox_pm2ap 8>;
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shmem = <&ap2pm_scmi_mem>, <&pm2ap_scmi_mem>;
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#address-cells = <1>;
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#size-cells = <0>;
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scmi_clk: protocol@14 {
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reg = <0x14>;
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#clock-cells = <1>;
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};
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};
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ap_to_tfa_scmi: scmi-1 {
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compatible = "arm,scmi-smc";
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arm,smc-id = <0xc2000001>;
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#address-cells = <1>;
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#size-cells = <0>;
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shmem = <&ap_tfa_scmi_mem>;
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smc_devpd: protocol@11 {
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reg = <0x11>;
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#power-domain-cells = <1>;
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};
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};
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};
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pmu-a520 {
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compatible = "arm,cortex-a520-pmu";
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_partition0>;
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};
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pmu-a720 {
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compatible = "arm,cortex-a720-pmu";
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_partition1>;
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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s5_gpio_apb_clk: clock-100000000 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <100000000>;
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clock-output-names = "s5_gpio_apb_clk";
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};
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soc@0 {
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compatible = "simple-bus";
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ranges = <0 0 0 0 0x20 0>;
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dma-ranges;
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#address-cells = <2>;
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#size-cells = <2>;
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i2c0: i2c@4010000 {
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compatible = "cdns,i2c-r1p14";
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reg = <0x0 0x04010000 0x0 0x10000>;
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clock-frequency = <400000>;
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clocks = <&scmi_clk CLK_TREE_FCH_I2C0_APB>;
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interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH 0>;
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status = "disabled";
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};
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i2c1: i2c@4020000 {
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compatible = "cdns,i2c-r1p14";
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reg = <0x0 0x04020000 0x0 0x10000>;
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clock-frequency = <400000>;
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clocks = <&scmi_clk CLK_TREE_FCH_I2C1_APB>;
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interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH 0>;
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status = "disabled";
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};
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i2c2: i2c@4030000 {
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compatible = "cdns,i2c-r1p14";
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reg = <0x0 0x04030000 0x0 0x10000>;
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clock-frequency = <400000>;
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clocks = <&scmi_clk CLK_TREE_FCH_I2C2_APB>;
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interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH 0>;
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status = "disabled";
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};
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i2c3: i2c@4040000 {
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compatible = "cdns,i2c-r1p14";
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reg = <0x0 0x04040000 0x0 0x10000>;
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clock-frequency = <400000>;
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clocks = <&scmi_clk CLK_TREE_FCH_I2C3_APB>;
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interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH 0>;
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status = "disabled";
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};
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i2c4: i2c@4050000 {
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compatible = "cdns,i2c-r1p14";
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reg = <0x0 0x04050000 0x0 0x10000>;
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clock-frequency = <400000>;
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clocks = <&scmi_clk CLK_TREE_FCH_I2C4_APB>;
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interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH 0>;
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status = "disabled";
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};
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i2c5: i2c@4060000 {
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compatible = "cdns,i2c-r1p14";
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reg = <0x0 0x04060000 0x0 0x10000>;
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clock-frequency = <400000>;
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clocks = <&scmi_clk CLK_TREE_FCH_I2C5_APB>;
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interrupts = <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH 0>;
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status = "disabled";
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};
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i2c6: i2c@4070000 {
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compatible = "cdns,i2c-r1p14";
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reg = <0x0 0x04070000 0x0 0x10000>;
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clock-frequency = <400000>;
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clocks = <&scmi_clk CLK_TREE_FCH_I2C6_APB>;
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interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH 0>;
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status = "disabled";
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};
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i2c7: i2c@4080000 {
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compatible = "cdns,i2c-r1p14";
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reg = <0x0 0x04080000 0x0 0x10000>;
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clock-frequency = <400000>;
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clocks = <&scmi_clk CLK_TREE_FCH_I2C7_APB>;
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interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH 0>;
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status = "disabled";
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};
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spi0: spi@4090000 {
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compatible = "cix,sky1-spi-r1p6", "cdns,spi-r1p6";
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reg = <0x0 0x04090000 0x0 0x10000>;
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clocks = <&scmi_clk CLK_TREE_FCH_SPI0_APB>,
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<&scmi_clk CLK_TREE_FCH_SPI0_APB>;
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clock-names = "ref_clk", "pclk";
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interrupts = <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH 0>;
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status = "disabled";
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};
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spi1: spi@40a0000 {
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compatible = "cix,sky1-spi-r1p6", "cdns,spi-r1p6";
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reg = <0x0 0x040a0000 0x0 0x10000>;
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clocks = <&scmi_clk CLK_TREE_FCH_SPI1_APB>,
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<&scmi_clk CLK_TREE_FCH_SPI1_APB>;
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clock-names = "ref_clk", "pclk";
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interrupts = <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH 0>;
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status = "disabled";
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};
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uart0: serial@40b0000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x0 0x040b0000 0x0 0x1000>;
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interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&scmi_clk CLK_TREE_FCH_UART0_FUNC>, <&scmi_clk CLK_TREE_FCH_UART0_APB>;
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clock-names = "uartclk", "apb_pclk";
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status = "disabled";
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};
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uart1: serial@40c0000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x0 0x040c0000 0x0 0x1000>;
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interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&scmi_clk CLK_TREE_FCH_UART1_FUNC>, <&scmi_clk CLK_TREE_FCH_UART1_APB>;
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clock-names = "uartclk", "apb_pclk";
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status = "disabled";
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};
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uart2: serial@40d0000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x0 0x040d0000 0x0 0x1000>;
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interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&scmi_clk CLK_TREE_FCH_UART2_FUNC>, <&scmi_clk CLK_TREE_FCH_UART2_APB>;
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clock-names = "uartclk", "apb_pclk";
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status = "disabled";
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};
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uart3: serial@40e0000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x0 0x040e0000 0x0 0x1000>;
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interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&scmi_clk CLK_TREE_FCH_UART3_FUNC>, <&scmi_clk CLK_TREE_FCH_UART3_APB>;
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clock-names = "uartclk", "apb_pclk";
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status = "disabled";
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};
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i3c0: i3c@40f0000 {
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compatible = "cdns,i3c-master";
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reg = <0x0 0x040f0000 0x0 0x10000>;
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#address-cells = <3>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&scmi_clk CLK_TREE_FCH_I3C0_APB>,
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<&scmi_clk CLK_TREE_FCH_I3C0_FUNC>;
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clock-names = "pclk", "sysclk";
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i3c-scl-hz = <400000>;
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i2c-scl-hz = <100000>;
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status = "disabled";
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};
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i3c1: i3c@4100000 {
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compatible = "cdns,i3c-master";
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reg = <0x0 0x04100000 0x0 0x10000>;
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#address-cells = <3>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&scmi_clk CLK_TREE_FCH_I3C1_APB>,
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<&scmi_clk CLK_TREE_FCH_I3C1_FUNC>;
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clock-names = "pclk", "sysclk";
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i3c-scl-hz = <400000>;
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i2c-scl-hz = <100000>;
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status = "disabled";
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};
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fch_gpio0: gpio-controller@4120000 {
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compatible = "cdns,gpio-r1p02";
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reg = <0x0 0x4120000 0x0 0x1000>;
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clocks = <&scmi_clk CLK_TREE_FCH_GPIO_APB>;
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interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH 0>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <32>;
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interrupt-controller;
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#interrupt-cells = <2>;
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status = "disabled";
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};
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fch_gpio1: gpio-controller@4130000 {
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compatible = "cdns,gpio-r1p02";
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reg = <0x0 0x4130000 0x0 0x1000>;
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clocks = <&scmi_clk CLK_TREE_FCH_GPIO_APB>;
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interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH 0>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <32>;
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interrupt-controller;
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#interrupt-cells = <2>;
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status = "disabled";
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};
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fch_gpio2: gpio-controller@4140000 {
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compatible = "cdns,gpio-r1p02";
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reg = <0x0 0x4140000 0x0 0x1000>;
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clocks = <&scmi_clk CLK_TREE_FCH_GPIO_APB>;
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interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH 0>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <32>;
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interrupt-controller;
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#interrupt-cells = <2>;
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status = "disabled";
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};
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fch_gpio3: gpio-controller@4150000 {
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compatible = "cdns,gpio-r1p02";
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reg = <0x0 0x4150000 0x0 0x1000>;
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clocks = <&scmi_clk CLK_TREE_FCH_GPIO_APB>;
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interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH 0>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <17>;
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interrupt-controller;
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#interrupt-cells = <2>;
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status = "disabled";
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};
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syscon: syscon@4160000 {
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compatible = "cix,sky1-system-control", "syscon";
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reg = <0x0 0x4160000 0x0 0x100>;
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#reset-cells = <1>;
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};
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iomuxc: pinctrl@4170000 {
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compatible = "cix,sky1-pinctrl";
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reg = <0x0 0x04170000 0x0 0x1000>;
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};
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mbox_ap2se: mailbox@5060000 {
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compatible = "cix,sky1-mbox";
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reg = <0x0 0x05060000 0x0 0x10000>;
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interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH 0>;
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#mbox-cells = <1>;
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cix,mbox-dir = "tx";
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};
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mbox_se2ap: mailbox@5070000 {
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compatible = "cix,sky1-mbox";
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reg = <0x0 0x05070000 0x0 0x10000>;
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interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH 0>;
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#mbox-cells = <1>;
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cix,mbox-dir = "rx";
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};
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ap2pm_scmi_mem: shmem@6590000 {
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compatible = "arm,scmi-shmem";
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reg = <0x0 0x06590000 0x0 0x80>;
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reg-io-width = <4>;
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};
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mbox_ap2pm: mailbox@6590080 {
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compatible = "cix,sky1-mbox";
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reg = <0x0 0x06590080 0x0 0xff80>;
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interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH 0>;
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#mbox-cells = <1>;
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cix,mbox-dir = "tx";
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};
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pm2ap_scmi_mem: shmem@65a0000 {
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compatible = "arm,scmi-shmem";
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reg = <0x0 0x065a0000 0x0 0x80>;
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reg-io-width = <4>;
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};
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|
|
mbox_pm2ap: mailbox@65a0080 {
|
|
compatible = "cix,sky1-mbox";
|
|
reg = <0x0 0x065a0080 0x0 0xff80>;
|
|
interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
#mbox-cells = <1>;
|
|
cix,mbox-dir = "rx";
|
|
};
|
|
|
|
mbox_sfh2ap: mailbox@8090000 {
|
|
compatible = "cix,sky1-mbox";
|
|
reg = <0x0 0x08090000 0x0 0x10000>;
|
|
interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
#mbox-cells = <1>;
|
|
cix,mbox-dir = "rx";
|
|
};
|
|
|
|
mbox_ap2sfh: mailbox@80a0000 {
|
|
compatible = "cix,sky1-mbox";
|
|
reg = <0x0 0x080a0000 0x0 0x10000>;
|
|
interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
#mbox-cells = <1>;
|
|
cix,mbox-dir = "tx";
|
|
};
|
|
|
|
pcie_x8_rc: pcie@a010000 {
|
|
compatible = "cix,sky1-pcie-host";
|
|
reg = <0x00 0x0a010000 0x00 0x10000>,
|
|
<0x00 0x2c000000 0x00 0x4000000>,
|
|
<0x00 0x0a000300 0x00 0x100>,
|
|
<0x00 0x0a000400 0x00 0x100>,
|
|
<0x00 0x60000000 0x00 0x00100000>;
|
|
reg-names = "reg", "cfg", "rcsu_strap", "rcsu_status", "msg";
|
|
ranges = <0x01000000 0x0 0x60100000 0x0 0x60100000 0x0 0x00100000>,
|
|
<0x02000000 0x0 0x60200000 0x0 0x60200000 0x0 0x1fe00000>,
|
|
<0x43000000 0x18 0x00000000 0x18 0x00000000 0x04 0x00000000>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
bus-range = <0xc0 0xff>;
|
|
device_type = "pci";
|
|
power-domains = <&smc_devpd SKY1_PD_PCIE_CTRL0>;
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0 0 0 0x7>;
|
|
interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<0 0 0 2 &gic 0 0 GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<0 0 0 3 &gic 0 0 GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<0 0 0 4 &gic 0 0 GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
msi-map = <0xc000 &gic_its 0xc000 0x4000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pcie_x4_rc: pcie@a070000 {
|
|
compatible = "cix,sky1-pcie-host";
|
|
reg = <0x00 0x0a070000 0x00 0x10000>,
|
|
<0x00 0x29000000 0x00 0x3000000>,
|
|
<0x00 0x0a060300 0x00 0x40>,
|
|
<0x00 0x0a060400 0x00 0x40>,
|
|
<0x00 0x50000000 0x00 0x00100000>;
|
|
reg-names = "reg", "cfg", "rcsu_strap", "rcsu_status", "msg";
|
|
ranges = <0x01000000 0x00 0x50100000 0x00 0x50100000 0x00 0x00100000>,
|
|
<0x02000000 0x00 0x50200000 0x00 0x50200000 0x00 0x0fe00000>,
|
|
<0x43000000 0x14 0x00000000 0x14 0x00000000 0x04 0x00000000>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
bus-range = <0x90 0xbf>;
|
|
device_type = "pci";
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0 0 0 0x7>;
|
|
interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<0 0 0 2 &gic 0 0 GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<0 0 0 3 &gic 0 0 GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<0 0 0 4 &gic 0 0 GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
msi-map = <0x9000 &gic_its 0x9000 0x3000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pcie_x2_rc: pcie@a0c0000 {
|
|
compatible = "cix,sky1-pcie-host";
|
|
reg = <0x00 0x0a0c0000 0x00 0x10000>,
|
|
<0x00 0x26000000 0x00 0x3000000>,
|
|
<0x00 0x0a0600340 0x00 0x20>,
|
|
<0x00 0x0a0600440 0x00 0x20>,
|
|
<0x00 0x40000000 0x00 0x00100000>;
|
|
reg-names = "reg", "cfg", "rcsu_strap", "rcsu_status", "msg";
|
|
ranges = <0x01000000 0x0 0x40100000 0x0 0x40100000 0x0 0x00100000>,
|
|
<0x02000000 0x0 0x40200000 0x0 0x40200000 0x0 0x0fe00000>,
|
|
<0x43000000 0x10 0x00000000 0x10 0x00000000 0x04 0x00000000>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
bus-range = <0x60 0x8f>;
|
|
device_type = "pci";
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0 0 0 0x7>;
|
|
interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<0 0 0 2 &gic 0 0 GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<0 0 0 3 &gic 0 0 GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<0 0 0 4 &gic 0 0 GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
msi-map = <0x6000 &gic_its 0x6000 0x3000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pcie_x1_0_rc: pcie@a0d0000 {
|
|
compatible = "cix,sky1-pcie-host";
|
|
reg = <0x00 0x0a0d0000 0x00 0x10000>,
|
|
<0x00 0x20000000 0x00 0x3000000>,
|
|
<0x00 0x0a060360 0x00 0x20>,
|
|
<0x00 0x0a060460 0x00 0x20>,
|
|
<0x00 0x30000000 0x00 0x00100000>;
|
|
reg-names = "reg", "cfg", "rcsu_strap", "rcsu_status", "msg";
|
|
ranges = <0x01000000 0x0 0x30100000 0x0 0x30100000 0x0 0x00100000>,
|
|
<0x02000000 0x0 0x30200000 0x0 0x30200000 0x0 0x07e00000>,
|
|
<0x43000000 0x08 0x00000000 0x08 0x00000000 0x04 0x00000000>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
bus-range = <0x00 0x2f>;
|
|
device_type = "pci";
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0 0 0 0x7>;
|
|
interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<0 0 0 2 &gic 0 0 GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<0 0 0 3 &gic 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<0 0 0 4 &gic 0 0 GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
msi-map = <0x0000 &gic_its 0x0000 0x3000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pcie_x1_1_rc: pcie@a0e0000 {
|
|
compatible = "cix,sky1-pcie-host";
|
|
reg = <0x00 0x0a0e0000 0x00 0x10000>,
|
|
<0x00 0x23000000 0x00 0x3000000>,
|
|
<0x00 0x0a060380 0x00 0x20>,
|
|
<0x00 0x0a060480 0x00 0x20>,
|
|
<0x00 0x38000000 0x00 0x00100000>;
|
|
reg-names = "reg", "cfg", "rcsu_strap", "rcsu_status", "msg";
|
|
ranges = <0x01000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000>,
|
|
<0x02000000 0x0 0x38200000 0x0 0x38200000 0x0 0x07e00000>,
|
|
<0x43000000 0x0c 0x00000000 0x0c 0x00000000 0x04 0x00000000>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
bus-range = <0x30 0x5f>;
|
|
device_type = "pci";
|
|
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0 0 0 0x7>;
|
|
interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<0 0 0 2 &gic 0 0 GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<0 0 0 3 &gic 0 0 GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<0 0 0 4 &gic 0 0 GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
msi-map = <0x3000 &gic_its 0x3000 0x3000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
gic: interrupt-controller@e010000 {
|
|
compatible = "arm,gic-v3";
|
|
reg = <0x0 0x0e010000 0 0x10000>, /* GICD */
|
|
<0x0 0x0e090000 0 0x300000>; /* GICR * 12 */
|
|
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW 0>;
|
|
#interrupt-cells = <4>;
|
|
interrupt-controller;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
|
|
gic_its: msi-controller@e050000 {
|
|
compatible = "arm,gic-v3-its";
|
|
reg = <0x0 0x0e050000 0x0 0x30000>;
|
|
msi-controller;
|
|
#msi-cells = <1>;
|
|
};
|
|
|
|
ppi-partitions {
|
|
ppi_partition0: interrupt-partition-0 {
|
|
affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
|
|
};
|
|
|
|
ppi_partition1: interrupt-partition-1 {
|
|
affinity = <&cpu4 &cpu5 &cpu6 &cpu7 &cpu8 &cpu9 &cpu10 &cpu11>;
|
|
};
|
|
};
|
|
};
|
|
|
|
s5_syscon: syscon@16000000 {
|
|
compatible = "cix,sky1-s5-system-control", "syscon";
|
|
reg = <0x0 0x16000000 0x0 0x1000>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
s5_gpio0: gpio-controller@16004000 {
|
|
compatible = "cdns,gpio-r1p02";
|
|
reg = <0x0 0x16004000 0x0 0x1000>;
|
|
clocks = <&s5_gpio_apb_clk>;
|
|
|
|
interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
ngpios = <32>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
s5_gpio1: gpio-controller@16005000 {
|
|
compatible = "cdns,gpio-r1p02";
|
|
reg = <0x0 0x16005000 0x0 0x1000>;
|
|
clocks = <&s5_gpio_apb_clk>;
|
|
|
|
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
ngpios = <10>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
s5_gpio2: gpio-controller@16006000 {
|
|
compatible = "cdns,gpio-r1p02";
|
|
reg = <0x0 0x16006000 0x0 0x1000>;
|
|
clocks = <&s5_gpio_apb_clk>;
|
|
|
|
interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
ngpios = <10>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
iomuxc_s5: pinctrl@16007000 {
|
|
compatible = "cix,sky1-pinctrl-s5";
|
|
reg = <0x0 0x16007000 0x0 0x1000>;
|
|
};
|
|
|
|
ap_tfa_scmi_mem: shmem@84380000 {
|
|
compatible = "arm,scmi-shmem";
|
|
reg = <0x0 0x84380000 0x0 0x80>;
|
|
reg-io-width = <4>;
|
|
};
|
|
};
|
|
|
|
timer {
|
|
compatible = "arm,armv8-timer";
|
|
interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt";
|
|
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
|
|
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
|
|
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
|
|
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>,
|
|
<GIC_PPI 12 IRQ_TYPE_LEVEL_LOW 0>;
|
|
};
|
|
};
|