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Marvell CN20K SoCs integrate a DDR Performance Monitoring Unit (PMU) associated with the DDR controller. The block provides hardware counters to monitor DDR traffic and performance events and is accessed via a dedicated MMIO region. The CN20K DDR PMU is functionally equivalent to the CN10K DDR PMU, with minor register offset differences. Signed-off-by: Geetha sowjanya <gakula@marvell.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Will Deacon <will@kernel.org> |
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| .. | ||
| amlogic,g12-ddr-pmu.yaml | ||
| apm,xgene-pmu.yaml | ||
| arm,ccn.yaml | ||
| arm,cmn.yaml | ||
| arm,coresight-pmu.yaml | ||
| arm,dsu-pmu.yaml | ||
| arm,ni.yaml | ||
| arm,smmu-v3-pmcg.yaml | ||
| fsl-imx-ddr.yaml | ||
| marvell-cn10k-ddr.yaml | ||
| marvell-cn10k-tad.yaml | ||
| riscv,pmu.yaml | ||
| spe-pmu.yaml | ||
| starfive,jh8100-starlink-pmu.yaml | ||