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16f212563f
Convert the Texas Instruments APLL clock bindings to DT schema. Signed-off-by: Eduard Bostina <egbostina@gmail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
90 lines
2.4 KiB
YAML
90 lines
2.4 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/ti/ti,apll-clock.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Texas Instruments APLL clock
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maintainers:
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- Eduard Bostina <egbostina@gmail.com>
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allOf:
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- $ref: /schemas/clock/clock.yaml#
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description:
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This binding assumes a register-mapped APLL with usually two selectable
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input clocks (reference clock and bypass clock), with analog phase locked
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loop logic for multiplying the input clock to a desired output clock.
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This clock also typically supports different operation modes (locked, low
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power stop etc.) APLL mostly behaves like a subtype of a DPLL, although
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a simplified one at that.
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properties:
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compatible:
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enum:
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- ti,dra7-apll-clock
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- ti,omap2-apll-clock
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"#clock-cells":
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const: 0
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clocks:
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minItems: 1
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maxItems: 2
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description: Link phandles of parent clocks (clk-ref and clk-bypass)
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reg:
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minItems: 2
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maxItems: 3
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description: |
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Address and length of the register set for controlling the APLL.
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It contains the information of registers in the following order:
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"control" - contains the control register offset
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"idlest" - contains the idlest register offset
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"autoidle" - contains the autoidle register offset (OMAP2 only)
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ti,clock-frequency:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: static clock frequency for the clock (OMAP2 only)
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ti,idlest-shift:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: bit-shift for the idlest field (OMAP2 only)
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ti,bit-shift:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: bit-shift for enable and autoidle fields (OMAP2 only)
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required:
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- compatible
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- "#clock-cells"
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- clocks
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- reg
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unevaluatedProperties: false
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examples:
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- |
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bus {
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#address-cells = <1>;
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#size-cells = <0>;
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clock@21c {
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#clock-cells = <0>;
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compatible = "ti,dra7-apll-clock";
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clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>;
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reg = <0x021c>, <0x0220>;
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};
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clock@500 {
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#clock-cells = <0>;
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compatible = "ti,omap2-apll-clock";
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clocks = <&sys_ck>;
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ti,bit-shift = <2>;
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ti,idlest-shift = <8>;
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ti,clock-frequency = <96000000>;
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reg = <0x0500>, <0x0530>, <0x0520>;
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};
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};
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