Jingyi Wang c800e4c8a6 dt-bindings: cache: qcom,llcc: Document Maili SoC ... Add documentation for the Last Level Cache Controller (LLCC) bindings for Qualcomm Maili SoC which is fully compatible with the one found on Qualcomm Hawi. Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260604-maili-llcc-v2-1-dd24f05bc197@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>		2026-07-07 21:38:18 -05:00
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andestech,ax45mp-cache.yaml	dt-bindings: cache: ax45mp: add 2048 as a supported cache-sets value	2025-08-28 17:34:45 +01:00
freescale-l2cache.txt
l2c2x0.yaml	dt-bindings: cache: l2c2x0: Add missing power-domains	2026-06-12 09:11:41 -05:00
marvell,kirkwood-cache.yaml	dt-bindings: cache: Convert marvell,{feroceon,kirkwood}-cache to DT schema	2025-05-13 15:42:27 +01:00
marvell,tauros2-cache.yaml	dt-bindings: cache: Convert marvell,tauros2-cache to DT schema	2025-05-13 15:43:02 +01:00
qcom,llcc.yaml	dt-bindings: cache: qcom,llcc: Document Maili SoC	2026-07-07 21:38:18 -05:00
sifive,ccache0.yaml	dt-bindings: cache: sifive,ccache0: add a pic64gx compatible	2025-11-17 23:44:12 +00:00
socionext,uniphier-system-cache.yaml
starfive,jh8100-starlink-cache.yaml	dt-bindings: cache: Add docs for StarFive Starlink cache controller	2024-05-28 12:34:11 +01:00