Commit Graph

74296 Commits

Author SHA1 Message Date
Tao Huang
3d11013d8b MALI: midgard: Kbuild: Fix src path
Make $(src) as absolute path if it isn't already, by prefixing $(srctree).
Fix build module with "O=dir".

Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I50a809faee21afd66d8f2025d05602a8a85293df
2021-07-27 15:04:15 +08:00
Tao Huang
d94eb2767e MALI: utgard: Kbuild: Fix src path
Make $(src) as absolute path if it isn't already, by prefixing $(srctree).
Fix build module with "O=dir".

Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I4e6d1f252e51956dc264e544ebbf7cf774a39c5d
2021-07-27 14:58:35 +08:00
Sandy Huang
31307243fa drm/rockchip: analogix_dp: register analogix_dp to rockchip_drm_sub_dev_list
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: Iae408b344ea17f1eaa3718b8f57fcd402de0a2d9
2021-07-23 11:36:15 +08:00
Sandy Huang
6cd7f48350 drm/rockchip: dsi: register mipi dsi to rockchip_drm_sub_dev_list
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I9dea09bb785344342875a9879b77edf8d8bb8639
2021-07-23 11:36:15 +08:00
Sandy Huang
e78097e89b drm/bridge: dw-mipi-dsi: add api to get connector
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: Id024b178bf936f0af3a782fe2c54fde661cce0da
2021-07-23 11:36:15 +08:00
Algea Cao
c4bac4aa0b drm/rockchip: Add hdmi shutdown interface
When system shutdown, shutdown interface will be called.
Hdmi should be disabled when system shutdown.

Change-Id: I09ec1d7d3801bf8a8277c91072fa09bd1b430809
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
2021-07-23 09:57:23 +08:00
Algea Cao
37fda45520 drm/bridge: dw_hdmi: initialize hdmi i2c when system resume
Change-Id: Ie9373517e255c91ded38a4e620d15d5cfd0bd9c4
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
2021-07-23 09:57:23 +08:00
Algea Cao
495a7777d6 drm: bridge: dw-hdmi: set hdmi ddc pin HI-Z when suspend
Set hdmi ddc pin HI-Z to save power.

Change-Id: Ic5e15cac43c486e7de6be8526daea9b36da68bc8
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
2021-07-23 09:57:23 +08:00
Huicong Xu
36549072d7 drm/rockchip: dw_hdmi: add power domain control
close pd when suspend, no when plug out because hotplug detect need it.

make hdmi probe before dp otherwise the shared power domain will be
close after dp probe and cause splash screen when starting kernel if
hdmi uboot logo display

Change-Id: I82ba1abdaf7567173df9ad900d57eca0e6be3932
Signed-off-by: Huicong Xu <xhc@rock-chips.com>
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
2021-07-23 09:57:23 +08:00
Bin Yang
901d4890ec drm/bridge: dw_hdmi: clear ih_mute register when system resume
HDMI PD is power off when system suspend, so ih_mute register
bit0 mute_all_interrupt will be reset to 1 when system resume.
HPD interrupt will be mask, that would cause hdmi plugin could
not be detected.

Change-Id: I3bf2e6116e902cd516a7ac69fbe8569ca943e853
Signed-off-by: Bin Yang <yangbin@rock-chips.com>
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
2021-07-23 09:57:01 +08:00
Algea Cao
5d73d163ad drm: rockchip: dw-hdmi: Introduce HCLK_VOP for RK3566/RK3568
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: Ifcc15490b135692d955500114b59cbf8c326cacd
2021-07-23 09:50:08 +08:00
Algea Cao
3a99549ccd drm: rockchip: dw-hdmi: Add clk hclk_vio
Change-Id: If117c63f97c2af0811d29f322188ddc24470eadb
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
2021-07-23 09:49:56 +08:00
Algea Cao
a22981924b drm: rockchip: dw-hdmi: Set hdmi output interface to HDMI0
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: Ia9c694f73c1fe9ae3bdb4d8774658dca566ef6c2
2021-07-23 09:49:49 +08:00
Shunqing Chen
31238b71f1 drm: rockchip: dw-hdmi: add RK3568 support
Change-Id: I24ec9a60d915b71281362b0b2d67fb8c288cdd14
Signed-off-by: Shunqing Chen <csq@rock-chips.com>
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
2021-07-23 09:49:43 +08:00
Algea Cao
96afb6b92d drm: rockchip: dw-hdmi: Add encoder mode set
Update hdmi phy ref clock in encoder mode set.

Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I8e1df8e3d9e4109e9beae5bdaaf82ea8cc070407
2021-07-23 09:49:34 +08:00
Shunqing Chen
25665e043a drm: rockchip: dw-hdmi: rename vpll_clk to accommodate more platforms
Change-Id: I6d5aaacc241add2bbd20f2e16f2b4ae798e1db6a
Signed-off-by: Shunqing Chen <csq@rock-chips.com>
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
2021-07-23 09:49:19 +08:00
Mark Yao
5e564157e3 drm/rockchip: dw_hdmi: move vpll set rate to encoder enable
Change-Id: I5cf7f32f15cf1ea3e85b69009615756be3809c5e
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
2021-07-23 09:49:08 +08:00
WeiYong Bi
a90aecefe5 drm/rockchip: dw_hdmi: Add support for rk3368
Change-Id: I6a49447a5edd53013ed81875f351089793914f77
Signed-off-by: WeiYong Bi <bivvy.bi@rock-chips.com>
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
2021-07-23 09:48:57 +08:00
Andy Yan
e9881c87d7 drm/rockchip: vop2: fix hdr delay number setting when port_mux is not at last
HDR window is fixed(not move in the overlay path with port_mux change)
and is the most slow window. And the bg is the fast. So other windows
and bg need to add delay number to keep align with the most slow window.
The delay number list in the trm is a relative value for port_mux set at
last level.

Change-Id: I731b909c0a3f483be081e16610536b4ce5b9b8b0
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
2021-07-20 16:48:22 +08:00
Andy Yan
355191f0e3 drm/rockchip: vop2: Disable all other multi area when disable area0
When area0 is disabled, all other sub multi area must be
disabled, or the win may run into unexpected situlation:
such as post_buf_empty or iommu fault.

Change-Id: I8a92e45849cfc31af029ba0e86562751be92ddbd
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
2021-07-20 16:48:12 +08:00
Andy Yan
e1c6772ef9 drm/rockchip: vop2: No register mirror win when only one vp used
when only one vp(crtc) is registered to drm, all the
plane->possible_crtc will be force set to this crtc.
this make current hwc think that all these planes can be
assigned to this crtc, but the mirror plane(rk3566 feature)
cant't be activated on the same crtc with source plane.

So if some boards only use one vp(crtc), don't register
mirror plane.

Change-Id: Ib25246cf44a0fc4caf98e7c6d21ebba18f1a6c88
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
2021-07-20 16:47:59 +08:00
Sandy Huang
23110bdcf0 drm/rockchip: vop2: rk356x three vp share one gamma
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: Iddaf85a902feaa1c2a6004a1b8c2f419135cd039
2021-07-20 16:47:28 +08:00
Sandy Huang
4d56f3cc51 drm/rockchip: vop2: Add vcnt event
Change-Id: If00eeee975d8f073d27ae584c096e6a7de1df95b
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
2021-07-20 16:41:43 +08:00
Sandy Huang
c0b956d7c7 drm/rockchip: drv: Add vcnt event
The vcnt event is similar to vblank event, but userspace can set the
time(which scan line) when the event occur.

This add a new event type: DRM_EVENT_ROCKCHIP_CRTC_VCNT userspace create
this event by ioctl DRM_IOCTL_ROCKCHIP_GET_VCNT_EVENT

Change-Id: If3da4bb29469ac7dc379e9462994aeda3202d3d2
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
2021-07-20 16:22:24 +08:00
Sandy Huang
2e79c5086d drm/rockchip: drv: add open/close function
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I5adad7f8ac7a03391c08b53ef8a931086520f2e9
2021-07-20 16:09:20 +08:00
Sandy Huang
e2355b4b8b drm/rockchip: drv: add iommu fault handler
move rockchip_register_crtc_funcs/rockchip_unregister_crtc_funcs
position by the way for easy to compare with linux 4.19

Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I7959f654d9a0d3ea24bb747446f36c649797e2e0
2021-07-20 16:09:16 +08:00
Sandy Huang
4f8318d63e drm/rockchip: drv: add rockchip_drm_get_sub_dev_type
before this commit, the DMC driver use drm_device_get_by_name() to get drm
connector info, now we use rockchip_drm_get_sub_dev_type() to instead of
it.

Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: Ief6546d933fbb49e46e6e8d2a99464eb5951e069
2021-07-20 14:52:51 +08:00
Sandy Huang
b441d298c9 drm/rockchip: drv: add rockchip_drm_add_modes_noedid
rockchip_drm_add_modes_noedid() used to get the following
recommend modes at rockchip platform when get edid failed:

the recommend modes is: 480p60, 576p50, 720p50, 720p60, 768p60,
1080p50, 1080p60 and 720p60 is the preferred mode.

Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I9c82b3949506a616e8c98bfa2d77532bdb870390
2021-07-20 14:52:51 +08:00
Sandy Huang
a430ff906a drm/rockchip: gem: Add GEM create ioctl support
Rockchip Socs have GPU, we need allocate GPU accelerated buffers.
So add special ioctls GEM_CREATE/GEM_MAP_OFFSET to support
accelerated buffers.

Change-Id: Ia4b13798aac97d16214da7a75a2479e6e334313a
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
2021-07-20 14:52:51 +08:00
Zhen Chen
6a2af737e9 Mali: midgard: Fix a runtime WARNING as below
[    4.128429] WARNING: CPU: 0 PID: 247 at drivers/gpu/arm/midgard/mali_kbase_mem_linux.c:1772 kbase_mmap+0x380/0xa78
...

Treat VM_FAULT_NOPAGE as success of calling vmf_insert_pfn().
Take https://android.googlesource.com/kernel/hikey-modules/+/refs/heads/android12-5.10/midgard/mali_kbase_mem_linux.c as a reference.

Fixes: 970017f88e ("MALI: midgard: Fix all compile errors under kernel 5.10")
Change-Id: Ie0562d8024e58031ba8126aab42dc7005f08b071
Signed-off-by: Zhen Chen <chenzhen@rock-chips.com>
2021-07-16 20:26:19 +08:00
Tao Huang
eceea1a746 MALI: midgard: Add _mali_profiling_control to rename.h
FATAL: modpost: drivers/gpu/arm/mali400/mali/mali: '_mali_profiling_control'
exported twice. Previous export was in drivers/gpu/arm/midgard/midgard_kbase.ko

Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: Ia75a4edce98dbf5f8d8cbc286c6e5c2faf99c295
2021-07-14 10:03:55 +08:00
Sandy Huang
3ee3c8c01e drm/rockchip: remove drm_atomic_set_property calls
drm_atomic_set_property isn't export function, so we set default prop
vale to instead of it.

Change-Id: I4acc6ddd045415aa180d467b45085609408e2447
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
2021-07-13 20:34:50 +08:00
Andy Yan
eefa1f67a0 drm/rockchip: vop2: Add uv offset for y mirror
Esmart/Smart should add offset in y mirror mode.

Change-Id: I5299543006c702c1492ee740460d0b7536e7d6e8
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
2021-07-13 20:34:50 +08:00
Sandy Huang
0084647e87 drm/rockchip: drv: update rockchip drm driver version to 3.0
linux 4.4:  1.0
linux 4.19: 2.0
linux 5.10: 3.0

Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I8f1d7f53ccbdcfd163343ff179271a466a9cc661
2021-07-12 15:01:19 +08:00
Sandy Huang
c910049be1 drm/rockchip: vop2: add more yuv format
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I30f4ca4ce7b9cfc0c3943bb547a57cb5d7547b6c
2021-07-12 15:01:19 +08:00
Sandy Huang
9fad8c5fa8 drm: drm_fourcc: add NV20 and NV30 format
DRM_FORMAT_NV20 and DRM_FORMAT_NV30 is a 2 plane format suitable for
linear layouts, this two format is similar to NV15 has no padding
between component, but NV15 is 4:2:0 sub-sampling, NV20 is 4:2:2
sub-sampling and NV30 is no-sampling.

The '20' and '30' suffix refers to the optimum effective bits per
pixel which is achieved.

Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I84da7e03125e675f274c6307128b4b7b307767cc
2021-07-12 15:01:19 +08:00
Guochun Huang
255e14f4b3 drm/bridge: dw-mipi-dsi: the lanes of dual-dsi is twice as much as max_data_lanes
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
Change-Id: I1666a320a08318f555b145281f4fc324893ebc59
2021-07-12 14:56:56 +08:00
Guochun Huang
292f792757 drm/rockchip: dsi: add support dual dsi
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
Change-Id: I6c929771a7f45c778f84f549e28cea74312ad9b8
2021-07-12 14:56:56 +08:00
Sandy Huang
402889ee5f drm/rockchip: vop2: close cluster sub win when main win is closed
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: Ifad854f2e70fe3487731f6cd1d3c41f2a512087e
2021-07-09 17:21:13 +08:00
Andy Yan
2309468102 drm/rockchip: vop2: Support disable Cluster sub win
Change-Id: Ia2f764992ce51ca61f6ba269083fa643509f58e1
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
2021-07-09 17:21:04 +08:00
Andy Yan
d19ffa72a4 drm/rockchip: vop2: Support set cursor win from dts
for example:

Use CLuster0 as cursor win for vp0.

&vp0 {
	cursor-win-id = <ROCKCHIP_VOP2_CLUSTER0>;
};

Change-Id: I10f7921928fbf7ff803c55a95cbce62df658fbed
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
2021-07-09 17:20:54 +08:00
Sandy Huang
30dd06d9b2 drm/rockchip: vop2: check plane state before check plane oetf
We have some plane not registered to drm core(Such as cluster
plane on some linux system), so they don't have pstate.

And also we don't need to check plane state for oetf for
a inactived plane(has no fb).

Change-Id: I909b665397c3df530ff0f466e0d654dcbb3f1a40
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
2021-07-09 17:20:45 +08:00
Sandy Huang
93f2587f47 drm/rockchip: vop2: only when have active win then need to wait win close
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: Ieaf6497a8597d5d6d3f4a0eb0169fba55c93b4e2
2021-07-09 17:20:37 +08:00
Sandy Huang
91b41a2818 drm/rockchip: vop2: use default sdr2hdr(1000nit) curve
keep sdr2hdr result consistent between VOP and GPU

Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I3ef6b289978d4b0c083d99e93d97a95b2e7f0b25
2021-07-09 17:20:24 +08:00
Sandy Huang
088fa736f9 drm/rockchip: vop2: fix csc config error when at hdr mode
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: Ide5b9deb13882a561765a2e2be660e3463d1764f
2021-07-09 17:18:29 +08:00
Sandy Huang
0f7ea21642 drm/rockchip: vop2: add more sdr2hdr scene
maybe appear the following scene for sdr2hdr:
1. one sdr layer      -> vop[sdr2hdr]   -> hdr output
2. one hdr layer      -> vop[bypass]  |
                                      | -> hdr output
   one/more sdr layer -> vop[sdr2hdr] |

Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I042baf68d36f6f9a089d81928c783e52a2b21499
2021-07-09 17:17:23 +08:00
Andy Yan
cab0d20056 drm/rockchip: vop2: Support set background color from userspace
Add a BACKGROUND property for each crtc.
8 bit for every color channel(r/g/b/y/u/v).

Change-Id: I9439bf16a8142e936508e843cc25b6263e2f661d
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
2021-07-09 17:16:34 +08:00
Andy Yan
e4c73bca35 drm/rockchip: vop2: Fix color key shift to 10bit
Fixes: 8c59d20b75 ("drm/rockchip: vop2: Add color key support")
Change-Id: I449f32eb9e69297b2c37feb85611a550310f2304
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
2021-07-09 17:16:01 +08:00
Sandy Huang
fd219584a9 drm/rockchip: vop2: add more debug info
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I9277ff4a0f363fdb53aed88a33007a31e6f47f4c
2021-07-09 17:14:47 +08:00
Sandy Huang
49dc2e264f drm/rockchip: vop2: use wait done bit instead of fs raw bit
the fs raw bit will be cleared by vop2_isr() fs irq and lead to
vop2_wait_for_fs_by_raw_status() time out, so we use
vop2_wait_for_fs_by_done_bit_status() to wait done bit from 1 to 0 is
more reliable.

Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: Ice35fb9bfe6c2ef7a49496b15b9f58bf93e95d4e
2021-07-09 17:13:51 +08:00