T3-p1 with 650mV output voltage is the best signal via the test.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Change-Id: I5c2bd3ab0c235f3079925a03a59c419ad37da485
On most of rockchip platforms, the usb2 phy lost power
during deep sleep. So we need to reset phy during pm
resume to recovery clock to usb controller.
When do sleeptest on rk3588 evb1, without this patch,
it may fail in ehci_resume or ohci_resume, because
the ehci/ohci controller can't get clock from usb2 phy.
Note that the phy reset is optional in devicetree, so
it needs to check the reset_control of phy before phy
reset operation to avoid unnecessary delay.
Fixes: ba8a6e65a7 ("phy: rockchip: inno_usb2: only reset phy if deassert iddq for rk3588")
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: I31dee9baea472d9e314eca6cb9f78b2aab0e5353
RV1126 PMU supports to enable USB interrupt as wakeup
source, include USB PHY irqs from OTG port and Host port.
In additionally, it needs to enable Host port wakeup in
GRF_SOC_CON0.
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: Ia4d2b868a42afb9fe35d444d5df557c3b6c12b37
Tuing pre-emphasis and turn off differential receiver in suspend mode
for rk3326s and px30s SoCs.
Fix some pc can not recognize the device when using 5m cable, so tuning
usb phy squelch trigger point configure to 100mv for px30s.
Signed-off-by: Jianwei Zheng <jianwei.zheng@rock-chips.com>
Change-Id: Ida216e8951c1f1dad19fa3ff4c31ede6a53b3458
The current code always reset the usb2 phy in the
rk3588_usb2phy_tuning(), this cause the usb core
reset the device which connected to the usb2 host
interface during pm resume. Actually, it only needs
to reset the phy when it exit from iddq mode, so
add this patch to reset phy more reasonably, and
avoid reset usb device during pm resume.
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: I296636321d0cbe6b7ee7be9bd1614237a34312e9
Set the PLL SCC ppm adjust signal to 3500ppm for better compatibility.
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: I80aca9cd53aa08944bb929156dc9474118679b47
https://source.android.com/security/bulletin/2022-01-01
CVE-2022-24958
CVE-2022-20136
CVE-2022-23960
CVE-2022-20141
CVE-2021-4154
CVE-2022-20132
* tag 'ASB-2022-06-05_12-5.10': (1188 commits)
BACKPORT: net/sched: cls_u32: fix netns refcount changes in u32_change()
UPSTREAM: io_uring: always use original task when preparing req identity
FROMLIST: remoteproc: Fix dma_mem leak after rproc_shutdown
FROMLIST: dma-mapping: Add dma_release_coherent_memory to DMA API
ANDROID: Update QCOM symbol list for __reset_control_get
ANDROID: vendor_hooks: Add hooks for mutex
BACKPORT: can: ems_usb: ems_usb_start_xmit(): fix double dev_kfree_skb() in error path
BACKPORT: can: usb_8dev: usb_8dev_start_xmit(): fix double dev_kfree_skb() in error path
ANDROID: GKI: Update symbols to symbol list
ANDROID: oplus: Update the ABI xml and symbol list
UPSTREAM: remoteproc: Fix count check in rproc_coredump_write()
BACKPORT: esp: Fix possible buffer overflow in ESP transformation
ANDROID: Fix the drain_all_pages default condition broken by a hook
UPSTREAM: Revert "xfrm: xfrm_state_mtu should return at least 1280 for ipv6"
UPSTREAM: xfrm: fix MTU regression
ANDROID: signal: Add vendor hook for memory reaping
FROMGIT: usb: gadget: uvc: allow for application to cleanly shutdown
FROMGIT: usb: dwc3: gadget: increase tx fifo size for ss isoc endpoints
UPSTREAM: usb: gadget: configfs: clear deactivation flag in configfs_composite_unbind()
FROMGIT: usb: gadget: uvc: remove pause flag use
...
Change-Id: Idf3eea3b21dc69c8189161c0e24744336431913a
Conflicts:
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
drivers/spi/spi-rockchip.c
drivers/usb/gadget/function/f_uvc.c
drivers/usb/gadget/function/uvc.h
drivers/usb/gadget/function/uvc_configfs.c
drivers/usb/gadget/function/uvc_queue.c
drivers/usb/gadget/function/uvc_video.c
sound/soc/rockchip/rockchip_i2s.c
https://source.android.com/security/bulletin/2022-04-01
CVE-2021-0707
CVE-2021-39800
CVE-2021-39801 (4.9 only)
CVE-2021-39802
* tag 'ASB-2022-04-05_12-5.10': (3832 commits)
ANDROID: GKI: Update symbols to abi_gki_aarch64_oplus
ANDROID: vendor_hooks: Reduce pointless modversions CRC churn
UPSTREAM: locking/lockdep: Avoid potential access of invalid memory in lock_class
ANDROID: mm: Fix implicit declaration of function 'isolate_lru_page'
ANDROID: GKI: Update symbols to symbol list
ANDROID: GKI: Update symbols to symbol list
ANDROID: GKI: Add hook symbol to symbol list
Revert "ANDROID: dm-bow: Protect Ranges fetched and erased from the RB tree"
ANDROID: vendor_hooks: Add hooks to for free_unref_page_commit
ANDROID: vendor_hooks: Add hooks to for alloc_contig_range
ANDROID: GKI: Update symbols to symbol list
ANDROID: vendor_hooks: Add hook in shrink_node_memcgs
ANDROID: GKI: Add symbols to symbol list
FROMGIT: iommu/iova: Improve 32-bit free space estimate
ANDROID: export walk_page_range and swp_swap_info
ANDROID: vendor_hooks: export shrink_slab
ANDROID: usb: gadget: f_accessory: add compat_ioctl support
UPSTREAM: sr9700: sanity check for packet length
UPSTREAM: io_uring: return back safer resurrect
UPSTREAM: Revert "xfrm: state and policy should fail if XFRMA_IF_ID 0"
...
Change-Id: Ic61ead530b99b10ffd535a358a48fe9bb8c33fd4
Conflicts:
drivers/android/Kconfig
drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
drivers/gpu/drm/rockchip/rockchip_vop_reg.c
drivers/i2c/busses/i2c-rk3x.c
drivers/media/i2c/imx258.c
drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
drivers/usb/dwc2/gadget.c
drivers/usb/gadget/function/uvc.h
lib/Kconfig.debug
1. Set different pre_emphasize strength for rv1106 and rv1103.
- Set pre_emphasize strength to 0x03 for cpu verison_0;
- Set pre_emphasize strength to 0x01 for cpu verison_1;
2. Bypass Squelch detector calibration to improve receiving
sensitivity.
- Before: E-17 248.7mv, E-16 112.6mv
- After: E-17 150mv, E-16 98.8mv
Note:
E-17 and E-16 is on page 3 of the "USB 2.0 Electrical Compliance Test Specification"
https://usb.org/document-library/usb-20-electrical-compliance-test-specification-version-107
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: I0d668b3d126583ada03d9675e0175f02537d915f
This patch adds bvalid control registers for RK3588 OTG1 USB2.0
PHY. Then RK3588 Type-C1 can support USB Charger detection if
the TYPEC1_USB20_VBUSDET is always pull up to 3.3V, note that
add property "rockchip,typec-vbus-det" in DTS u2phy1_otg node.
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: Icee95425fa2671a02bdc999339437009469100c3
Modify the dts for the combophy:
1. assign clock to 100MHz
2. add "rockchip,ext-refclk"
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Change-Id: I72c125ac6aa42dcf00761f32e20b10042fd9985d
Don't set the frequency to 1.25 times in hdptx_phy_clk_set_rate,
hdptx_ropll_cmn_config has already done this.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: Ic9728308ca88edb158f11f70af6d9d7b95825ef9
It can avoid potential build warn/error when CONFIG_DEBUG_FS
is not set. And also fix the following warning:
drivers/phy/rockchip/phy-rockchip-inno-usb3.c:297:5: warning: no previous prototype for ‘rockchip_u3phy_debugfs_init’ [-Wmissing-prototypes]
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: Ia5f8c0484f2aea53ba6b9eba0b5c8a68b9fc350e
The error code is missing in this code scenario, add the error code
'PTR_ERR(provider)' to the return value ret.
Eliminate the follow smatch warning:
drivers/phy/rockchip/phy-rockchip-inno-usb3.c:937 rockchip_u3phy_probe() warn: missing error code 'ret'
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: If534350cdae1ee09b210c0d475aa2b8673dc7c64
For Type-C scene, the TCPM notify the USB role to the USB
controller driver. However, the USB2-PHY is imperceptible.
So use submode to get the desired USB role from the USB
controller driver. Later, we can use the phy_set_mode_ext
in the USB controller driver to pass the desired USB role
to USB2-PHY.
With this patch, it can avoid to do battery charger detection
if the Type-C USB role is Host.
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: I37d3a43d5e0e82e37d45e2e49fb19c4add595b40
In uboot, a device can't be used as both phy device and clock
device. So It better to register a child device as clock device.
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: I6d06f3c3b0f0b48741a5c53f51df1766b2cb0740
This configuration is required for Gen1 l1ss support.
Change-Id: I921d1551dbbb4e85f823ce9ce0abbb96198d2ccf
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Tuning pre-emphasis and other properties for RK3308BS SoCs.
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Change-Id: If7bb89c04a487c54bcca81d2cdaa9ee9bb26533f
The otg port on Rockchip platforms can be designed in
three different hardware circuits with Type-A interface.
1. RK3588 EVB2 Type-A OTG0 port with vbus is controlled
by gpio, and vbus is always in high level.
2. RV1106 EVB1 Type-A OTG port with standard vbus designed
that vbus isn't always on, and just depends on the OTG
mode, that is, when the OTG port work as device mode,
the vbus is supplied by Host, when the OTG port work
as host mode, the vbus is always on.
3. RV1103 EVB1 Type-A OTG port has no vbus pin, and we set
the utmi_bvalid of phy to high from GRF software control.
In this case, the utmi_bvalid status register is in low
level, so we can't use the utmi_bvalid status to check the
utmi_bvalid for RV1103.
In order to support the above three application scenarios
for Type-A OTG port, especially phy runtime suspend control
for device mode, we need this patch.
With this patch, we can fix the following two issues:
1. RV1106 EVB1 Type-A OTG port can't enter phy suspend if
no usb cable connected.
2. RV1103 failed to switch to device mode by "otg_mode"
node, because phy enter suspend unexpectedly.
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: Ia0d388345a4768a721a7e289956bca9684f69a36
This patch fixes the following compile warning:
drivers/phy/rockchip/phy-rockchip-inno-usb2.c:1225:3: warning: Value stored to 'sch_work' is never read
drivers/phy/rockchip/phy-rockchip-inno-usb2.c:1235:4: warning: Value stored to 'sch_work' is never read
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: I053f5775b28707a45530405084e3df827edde882
On RK3588 platform, the USB Host port may miss disconnect
falling edge irq which is used to detect usb device plug in.
This always happens in the following two cases:
1. For RK3588 ARM PC, boot system from U Disk which connected
the USB2 Host port (EHCI & OHCI Controller);
2. For RK3588 EVB, increase the disconnect filer counter to
0xF4240 in the reg USB2PHY_GRF_DIS_CON. That is, the
disconnect rising/falling irq filter time is set to 10ms
depend on the 100MHz pclk.
In this case, we can clear the host_disconnect state depend
on the linestate irq which also means that an usb device is
connecting to the port.
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: Iadde3278c3383c0d477a0b9998871a5a1f5fe206
For linestate irq as a wakeup source, we need to reconfigure the
linestate filter value base on 32KHz clk at suspend time, and restore
it to the default when the system resume.
By the way, set the grf to handle the phy status when the system
suspend, which can support the linestate wakeup even the PD of the
USB controller was off for RK3588 OTG1 port.
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Change-Id: I630855981082298d079d9c713029a7e3093b09cd
According to the new simulation result, we need to update the
phy configuration to cover different corner of rv1106 and rv1103.
1. Always enable pre-emphasis in SOF & EOP & chirp & non-chirp state;
2. Set Tx HS pre_emphasize strength to 3'b010;
3. Set 45ohm HS ODT value to 5'b10111 for better Rx ODT resistance.
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: I9faca9d35124122faf5a35c78f9ee13fd9c24bba
This update fix link fail because of RX signal on rk356x.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Change-Id: I7380f9ff0dfb351618fc09e543f676968b1f3ec9
RK3568 usb phy0 and phy1 linestate irq can be set as
wakeup source, but the default linestate filter time
is based on the usb phy grf pclk 100MHz. So it needs
to reconfigure the linestate filter time base on 32KHz
clk when enter deep sleep.
In addition, it needs to enable the host port (usb3
host1 and usb2 host1) wakeup irq because of legacy
reason.
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Change-Id: I9151d49721e8e9d917fdb51228f3ca2627090156
This is the best setting for internal clock which enable SSC mode.
Note for use this setting:
- Enable ssc in dts;
- modify to use 24M clock in dts.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Change-Id: Ia6db793dd8bf016985f4771ee1baac14449ae5b1
According to HW signal test, the T3 parameter is the best setting for
non-SSC mode, need to co-work with PPLL and DIV PF10.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Change-Id: I3b701f714bd63e08bb5d47046c37bba6701c4f8a
This default usb2 phy configuration of rv1106 and rv1103
isn't the best for HS signal quality. We should tuning
phy to get better HS eye height and slew rate.
And this patch also decrease the Rx squelch trigger point
for better compatibility.
Change-Id: Ie0356ac8f1250a820eddc2076c7258c60c0f3910
Signed-off-by: William Wu <william.wu@rock-chips.com>
Add three helpers phy_clear/set/update_bits() for registers operation.
Change-Id: Ie11d355ca1d8856baced39c2caf82e143284e5a3
Signed-off-by: William Wu <william.wu@rock-chips.com>
[ Upstream commit 3153fa38e3 ]
According to the comment of the function phy_mipi_dphy_get_default_config(),
it uses minimum D-PHY timings based on MIPI D-PHY specification. They are
derived from the valid ranges specified in Section 6.9, Table 14, Page 41
of the D-PHY specification (v1.2). The table 14 explicitly mentions that
the minimum T-LPX parameter is 50 nanoseconds and the minimum TA-SURE
parameter is T-LPX nanoseconds. Likewise, the kernel doc of the 'lpx' and
'ta_sure' members of struct phy_configure_opts_mipi_dphy mentions that
the minimum values are 50000 picoseconds and @lpx picoseconds respectively.
Also, the function phy_mipi_dphy_config_validate() checks if cfg->lpx is
less than 50000 picoseconds and if cfg->ta_sure is less than cfg->lpx,
which hints the same minimum values.
Without this patch, the function phy_mipi_dphy_get_default_config()
wrongly sets cfg->lpx to 60000 picoseconds and cfg->ta_sure to 2 * cfg->lpx.
So, let's correct them to 50000 picoseconds and cfg->lpx respectively.
Note that I've only tested the patch with RM67191 DSI panel on i.MX8mq EVK.
Help is needed to test with other i.MX8mq, Meson and Rockchip platforms,
as I don't have the hardwares.
Fixes: dddc97e823 ("phy: dphy: Add configuration helpers")
Cc: Andrzej Hajda <andrzej.hajda@intel.com>
Cc: Neil Armstrong <narmstrong@baylibre.com>
Cc: Laurent Pinchart <Laurent.pinchart@ideasonboard.com>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Cc: Vinod Koul <vkoul@kernel.org>
Cc: Heiko Stuebner <heiko@sntech.de>
Cc: Maxime Ripard <mripard@kernel.org>
Cc: Guido Günther <agx@sigxcpu.org>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Link: https://lore.kernel.org/r/20220216071257.1647703-1-victor.liu@nxp.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
If dp send data by aux channel too fast after phy power on,
the aux may be not ready which will cause aux error. Adding
delay to avoid this issue.
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: I92075e729e637078456ae67897dfb1cbda5da1cb
When DP output in Tyep-C interface, HPD and HPD IRQ info are
send by PD message, and transfer to phy by mux set callback
function. The usbdp phy need tell the DP controller not only
the HPD info, but also HPD IRQ info.
According to DP Standard 1.4a 3.3 section, the HPD IRQ pulse
width should be in the range from 0.5 ms to 1 ms, setting
the low level time between 750 us nad 800 us to satisfied
the specification.
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: Ie6d6d0537e6633e6e5f12119ceafc4109e32e74e
