Document the iW-RainboW-G23S single board computer device tree bindings,
listing it as a supported board.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add support for iWave iW-RainboW-G23S single board computer based on
RZ/G1C.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The initial R8A77470 SoC device tree including CPU0, GIC, timer, SYSC, RST,
CPG, and the required clock descriptions.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Sort the subnodes of the soc node to improve maintainability.
The sort has been done alphabetically with the node name as the key.
This patch should not introduce any functional change.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
The current practice is to not group clocks under a "clocks" subnode,
but just put them together with the other on-SoC devices.
As per updates for R-Car Gen2 SoCs by Geert Uytterhoeven.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Sort the subnodes of the soc node to improve maintainability.
The sort key is the address on the bus with instances of the same
IP block grouped together and sorted alphabetically.
This patch should not introduce any functional change.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Add soc node to represent the bus and move all nodes with a base address
into this node. This is consistent with handling of R-Car Gen3 and Gen2
SoCs in mainline. It is intended to migrate other Renesas ARM-based
SoCs to this scheme.
The ordering is derived from simply moving each node with an address up to
before any nodes without a base address that occur before the soc node. To
improve maintainability follow-up patches will sort subnodes of both the
new soc node and the root node.
This patch should not introduce any functional change.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Add support for R-Car E3 (R8A77990) to the R-Car RST driver.
This driver is needed for the clock driver to work.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[shimoda: rebase]
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Enable low-level debugging support for RZ/G1C (r8a77470). RZ/G1C uses
SCIF1 for the debug console.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add the RZ/N1 Family (Part #R9A06G0xx) ARCH config to the rest of
the Renesas SoC collection.
Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add minimal support for the RZ/G1C (R8A77470) SoC.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add support for RZ/G1C (R8A77470) SoC power areas to the R-Car SYSC
driver.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add support for identifying the RZ/G1C (r8a77470) SoC.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This patch is just wrong, sorry. I was trying to fix a static checker
warning and misread the code. The reference taken in macsec_newlink()
is released in macsec_free_netdev() when the netdevice is destroyed.
This reverts commit 5dcd840088.
Reported-by: Laura Abbott <labbott@redhat.com>
Fixes: 5dcd840088 ("macsec: missing dev_put() on error in macsec_newlink()")
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Acked-by: Sabrina Dubroca <sd@queasysnail.net>
Signed-off-by: David S. Miller <davem@davemloft.net>
Move tempmon node from soc node to root node.
tempmon node does not have any register properties and thus
shouldn't be placed on the bus.
This fixes the following build warning with W=1:
arch/arm/boot/dts/imx7d-cl-som-imx7.dtb: Warning (simple_bus_reg): Node /soc/aips-bus@30000000/tempmon missing or empty reg/ranges property
Fixes: de25b9bb4a ("ARM: dts: imx7s: add temperature monitor support")
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Update SAI select input daisy chain value according to
Reference Manual.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The HB onboard audio currently makes use of the imx-audio-sgtl5000
binding. This binding does not support auxiliary audio devices such
as external amplifiers. The simple-audio-card binding does support
this property which allows systems incorporating the HB to add an
auxiliary device that's attached to the HB audio jack with an
overlay. Convert the HB onboard audio to use simple-audio-card for
this additional flexibility.
Signed-off-by: Matt Porter <mporter@konsulko.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The A33 has a MIPI-DSI block, along with its D-PHY. Let's add it in order
to use it in the relevant boards.
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Commit 45e01f401a ("ARM: dts: sunxi: Switch MMC nodes away from
cd-inverted property") changed most of the sunxi boards away from using
the cd-inverted property in MMC nodes. However, the
sun7i-a20-olimex-som204-evb board which got merged concurrently with
that commit is now using cd-inverted. Switch it away from using
cd-inverted to be consistent with rest of the sunxi boards.
Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Banana Pi M2 Berry has an on-board USB Hub that provides 4 USB Type-A
ports, and it's connected to the USB1 port of the SoC.
Enable it.
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
The CHPN0001 ACPI device has a _CID of PNP0C50 and even has the _DSM to
get the HID descriptor address, but it is not a HID device at all.
It uses its own protocol which is handled by the (still being upstreamed)
chipone_icn8505 driver. I guess the _CID and the _DSM are the result of
a copy and paste job when the vendor was building the ACPI tables.
Before this patch the i2c_hid_driver's probe function will fail with a
"hid_descr_cmd failed" error.
This commit makes the i2c_hid_driver's probe function instead silently
ignored devices with an ACPI id of CHPN0001.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Jiri Kosina <jkosina@suse.cz>
Log an error in all error paths of i2c_hid_acpi_pdata() instead of having
the caller log a generic error.
This is a preparation patch for allowing i2c_hid_acpi_pdata() to fail
silently under certain conditions.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Jiri Kosina <jkosina@suse.cz>
Add clocks in iommu nodes, since we are going to control clocks in
rockchip iommu driver.
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add the usb3 phyter for the USB3.0 OTG controller.
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reference clock is needed for pcie_phy, not pcie controller.
Actually pcie_phy doesn't need this since rk3399 clock driver
already take care of this.
Suggested-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Vicente Bergas <vicencb@gmail.com>
Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The PCIe signals are routed through the connector to the baseboard.
Signed-off-by: Vicente Bergas <vicencb@gmail.com>
Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
These clocks do not assign default clock frequency, and use the
default cru register value to get frequency, so if cpll increase
frequency, these clocks also increase their frequency, that may
exceed their signed off frequency. So assign default clock for
them to avoid it.
NOTE: on none of the boards currently in mainline do we expect
CPLL to be anything other than 800 MHz, but some future boards
might have it. It's still good to be explicit about the clock
rates to make diffing against future boards easier and also to
rely less on BIOS muxing.
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Commit c301b327ae ("arm64: dts: rockchip: add usb3-phy otg-port
support for rk3399") caused a regression regarding the USB3. During
boot, the following message appears a few times:
dwc3: failed to initialize core
The driver is deferred waiting for the typec-phy, but this never
happens beause is disabled. So, enable it.
The offending commit was reverted in 4.16-rc but can be re-applied
after enabling the typec phys.
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Commit c301b327ae ("arm64: dts: rockchip: add usb3-phy otg-port
support for rk3399") caused a regression regarding the USB3. During boot,
the following message appears a few times:
dwc3: failed to initialize core
The driver is deferred waiting for the typec-phy, but this never happens
beause is disabled. So, enable it.
The offending commit was reverted in 4.16-rc but can be re-applied
after enabling the typec phys.
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Commit c301b327ae ("arm64: dts: rockchip: add usb3-phy otg-port
support for rk3399") caused a regression regarding the USB3. During boot,
the following message appears a few times:
dwc3: failed to initialize core
The driver is deferred waiting for the typec-phy, but this never happens
beause is disabled. So, enable it.
The offending commit was reverted in 4.16-rc but can be re-applied
after enabling the typec phys.
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Commit c301b327ae ("arm64: dts: rockchip: add usb3-phy otg-port
support for rk3399") caused a regression regarding the USB3 type-A port.
During boot, the following message appears a few times:
dwc3: failed to initialize core
The driver is deferred waiting for the typec-phy, but this never happens
bceause is disabled. So, enable it.
The offending commit was reverted in 4.16-rc but can be re-applied
after enabling the typec phys.
Reported-by: Vicente Bergas <vicencb@gmail.com>
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Tested-by: Vicente Bergas <vicencb@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The minnie devices comes with an AUO B101EAN01 panel which is different
from default veyron devices, thus the power on/off timing sequence is
slightly different. The datasheet specifies a pwm delay of 200 ms, so
update the PMW delay proprieties accordingly.
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Acked-by: Pavel Machek <pavel@ucw.cz>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
For veyron the binding should provide both PWM timings, the delay between
you enable the PWM and set the enable signal, and the delay between you
disable the PWM signal and clear the enable signal. Update the binding
accordingly, in this case the panels connected to the veyron boards have
a symmetric power sequence, hence the same value is used.
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Acked-by: Pavel Machek <pavel@ucw.cz>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add clocks in iommu nodes, since we are going to control clocks in
rockchip iommu driver.
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The CLK_O_SEL default is synchronous to XI input clock, which is 25 MHz.
Set CLK_O_SEL to channel A transmit clock so we have 125 MHz on CLK_OUT.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The AB8540 was an evolved version of the AB8500, but it was never
mass produced or put into products, only reference designs exist.
The upstream support was never completed and it is unlikely that
this will happen so drop the support for now to simplify
maintenance of the AB8500.
Cc: Loic Pallardy <loic.pallardy@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
The freq parameter indicates the physical frequency of an actual
input clock or a desired frequency of an output clock for HCKT/R.
It should never be passed 0. This might cause Division-by-zero.
So this patch adds a check to fix it.
Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
The emu10k1 fx8010 code allocates each irq resource dynamically and
links to the list at PCM trigger callback. Due to the nature of
trigger callback, the allocation is done with GFP_ATOMIC, hence it
may fail more often. Moreover, the irq resource isn't big at all, and
using the kmalloc for this won't save many bytes, either.
This patch removes the dynamic allocation and embeds the irq resource
into struct snd_emu10k1_fx8010_pcm.irq field instead of keeping a
pointer. As a result, it simplifies the code and removes the
unnecessary GFP_ATOMIC usage.
Signed-off-by: Takashi Iwai <tiwai@suse.de>
The uid and die temperature can be read out on the ADIN7 using
input mux. Map uid and die temperature sensor to channels 16
and 17.
Signed-off-by: Andrey Gusakov <andrey.gusakov@cogentembedded.com>
Acked-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
save_mixer_state() is called in a sleepable context, so it's safe to
allocate with GFP_KERNEL instead of the current GFP_ATOMIC. The
GFP_ATOMIC usage must have been based on an incorrect assumption in
the very old code base.
Signed-off-by: Takashi Iwai <tiwai@suse.de>
Reloading fw causes an audiable popping sound, we can avoid this
by not reloading if the samplerate is the same as before.
Signed-off-by: Danny Smith <dannys@axis.com>
Signed-off-by: Robert Rosengren <robert.rosengren@axis.com>
Acked-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Mark Brown <broonie@kernel.org>
This patch is used to tell kernel that new VIA HDAC controller also
support no-snoop path.
[ minor coding style fix by tiwai ]
Signed-off-by: David Wang <davidwang@zhaoxin.com>
Cc: <stable@vger.kernel.org>
Signed-off-by: Takashi Iwai <tiwai@suse.de>
snd_ad1889_ac97_ready() is never called in atomic context.
The call chain ending up at snd_ad1889_ac97_ready() is:
[1] snd_ad1889_ac97_ready() <- snd_ad1889_ac97_xinit() <-
snd_ad1889_ac97_init() <- snd_ad1889_probe()
snd_ad1889_probe() is only set as ".probe" in struct pci_driver.
This function is not called in atomic context.
Despite never getting called from atomic context, snd_ad1889_ac97_ready()
calls mdelay for busy wait.
This is not necessary and can be replaced with usleep_range to
avoid busy waiting.
This is found by a static analysis tool named DCNS written by myself.
Signed-off-by: Jia-Ju Bai <baijiaju1990@gmail.com>
Signed-off-by: Takashi Iwai <tiwai@suse.de>
