Use the HPD state machine state in detect instead of HPD_STATUS.
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: I9e6b14c819fa29dd38101340e40334f050832524
https://source.android.com/security/bulletin/2021-12-01
CVE-2021-33909
CVE-2021-38204
CVE-2021-0961
* tag 'ASB-2021-12-05_12-5.10': (3010 commits)
ANDROID: workqueue: export symbol of the function wq_worker_comm()
ANDROID: GKI: Update symbols to symbol list
ANDROID: vendor_hooks: Add hooks for binder proc transaction
ANDROID: GKI: Add symbols abi for USB IP kernel modules.
ANDROID: GKI: Fix file mode on mtk abi file
UPSTREAM: erofs: fix deadlock when shrink erofs slab
ANDROID: init_task: Init android vendor and oem data
UPSTREAM: sched/core: Mitigate race cpus_share_cache()/update_top_cache_domain()
ANDROID: Update symbol list for mtk
UPSTREAM: erofs: fix unsafe pagevec reuse of hooked pclusters
UPSTREAM: erofs: remove the occupied parameter from z_erofs_pagevec_enqueue()
UPSTREAM: usb: dwc3: gadget: Fix null pointer exception
ANDROID: fips140: support "evaluation testing" builds via build.sh
FROMGIT: sched/scs: Reset task stack state in bringup_cpu()
ANDROID: dma-buf: heaps: fix dma-buf heap pool pages stat
ANDROID: ABI: Add several spi_mem related symbols
UPSTREAM: spi: spi-mem: add spi_mem_dtr_supports_op()
ANDROID: gki_defconfig: enable CONFIG_SPI_MEM
ANDROID: ABI: Add several iio related symbols
ANDROID: ABI: Update symbol list for IMX
...
Change-Id: I09cddc92fa34553b944e62cc5cbbba94a84e5437
Conflicts:
arch/arm/boot/dts/rk322x.dtsi
arch/arm64/boot/dts/rockchip/rk3399.dtsi
drivers/dma-buf/heaps/system_heap.c
drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
drivers/gpu/drm/rockchip/rockchip_drm_vop.c
drivers/gpu/drm/rockchip/rockchip_lvds.c
drivers/gpu/drm/rockchip/rockchip_vop_reg.c
drivers/mtd/nand/spi/core.c
drivers/pci/controller/pcie-rockchip-host.c
drivers/soc/rockchip/Kconfig
drivers/usb/dwc3/core.c
drivers/usb/dwc3/core.h
RK3588 does not currently support this property.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: Iddb898bc044a3f2aa07b27506593b2c56f096e16
When a new connector is added to current routing in clone mode,
the new connector doesn't have mode_changed=true set. This
incorrect programming sequence causes .mode_set call mismatches
to occur in the new stream.
So move the mode_set code to other callback.
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: I90f50882057c63f702cf390fb7bfeed088575324
Use the definition of MEDIA_BUS_FMT_XXX instead of the
definition of sii902x_bus_format.
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: I72b4d92a1704f98f437a80d2a8afe16d9f6b003f
Fixes: f9e002e86f ("drm/rockchip: dw-dp: Add full output bus format support")
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: Ib644ce28a5963082989e5345f046aca591c63166
The drm core will disable than enable a crtc when is marked as
connectors_changed.
But when we attach a writeback connector to a running
crtc, we really don't need this disable/enable, which
will black a running screen.
Change-Id: I636615f27424bc60496ffc487c218f60fb95d719
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Some times we want change a overlay plane defined in vop2_reg
to primary plane.
Change-Id: I5f563fb258a66278255be762ebdfca21b51aabd1
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
after this commit, axi id is used as the following rules:
AXI0
Cluster0:
win0: 0x2，0x3
win1: 0x4，0x5
Cluster1:
win0: 0x6，0x7
win1: 0x8，0x9
Esmart0: 0xa, 0xb
Esmart1: 0xc, 0xd
Lut: 0xe[for vp0/2, will be used at different time]
AXI1:
Cluter2:
win0: 0x2，0x3
win1: 0x4，0x5
Cluster3:
win0: 0x6，0x7
win1: 0x8，0x9
Esmart2: 0xa，0xb
Esmart3: 0xc, 0xd
Lut: 0x1[for vp1]
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: Iae865835e49ba8ca0197b0f015d7709cba23e8b3
Support hdmi frl mode and dsc function.
Support max 8K-60Hz RGB 10bit output.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: Ibc2d48e2b25bc94e4be7ffa9703c400436bdee36
Replace IOMMU_TLB_SHOT_ENTIRE by shootdown_entire defined in
iommu DT node for clean IOMMU framework code and more convenient
for masters. The master should call iommu_flush_iotlb_all to
zap cache manually.
Signed-off-by: Simon Xue <xxm@rock-chips.com>
Signed-off-by: Herman Chen <herman.chen@rock-chips.com>
Change-Id: I5feab72fa12782d0715ad84a98cbd96a88bcd598
for vp2/vp3, we can use hardware or software TE to sync with panel ram,
but for vp1->dsc1->dsc1 path, we only can use software TE to sync with panel
ram.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
Change-Id: I0f54723c5c1c45916e669ce21819a127dc5b415d
Fixes: ca885383eb ("drm/rockchip: dw-dp: support dynamic binding to different vp port")
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: I94654e6eb916d688d9fe46544f60bd02e8d8cb7b
ACR located at Packet Scheduler which belongs to VIDQPCLK domain.
So, the related clk should be enabled before register access.
Actually, There are three CLK domain (AUDCLK, VIDQPCLK, LINKQPCLK)
related to Audio. So, do check clk status before config audio.
Maybe the better way should be spliting hdmi regmap into several parts
which managed by related clk domain in future.
e.g.
devm_regmap_init_mmio_clk(dev, "aud", regs, AUD_REGBANK);
devm_regmap_init_mmio_clk(dev, "vidqp", regs, VIDQP_REGBANK);
devm_regmap_init_mmio_clk(dev, "linkqp", regs, LINKQP_REGBANK);
...
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: Ib497d92a73d99d9f38c4617f615f02c705b82ae7
This reverts commit 6b7fb9a6c9.
The audio regbank of hdmi-qp is drived by audio interface clk, and had
fixed by commits as follows:
[1] 3a7f369b5c ("arm64: dts: rockchip: rk3588: Add aud clk for hdmi nodes")
[2] e108ff9f6f ("drm/rockchip: dw_hdmi: Handle aud clk for hdmi qp")
OTOH, to make android hal happy, we still allow to access hdmi audio even
hdmi is plugged out.
"hdmi-audio-codec: ASoC: error at snd_soc_dai_startup on i2s-hifi: -19"
Android/Linux should reopen hdmi sound card depends on HPD plug event
to bring back to normal state.
Change-Id: I654fe18a04b750f57c8bd52ef4948a476bc1fa50
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
The K will be set 2 in YUV420 output mode, so we
don't need to handle YUV420 for DisplayPort.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Change-Id: I8f42536735e65c82705d58382f1db2b2994d741b
Make hwc work correct when handle a 8K input source
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Change-Id: I77ee3c13f5c884fbdd9eec72b02998e10bbc3425
- Only check link retrain in short hpd pulse
- Always do link train in modeset
- Fix link retrain condition
- Add sink count check
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: Ifed1d706dcda5ac79322271ec59c2f1a5a79262b
Parse and set assigned clocks configuration at the child node level.
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: I745090ebc2a3531c51557600fdb69867d7216684
According to the application scenario, DP0/DP1 may be bind to the
same vp port, or different vp port. The corresponding bit in output_if
needs to be set or cleared correctly.
Change-Id: I880946d0c61a209d5a16ff7d2aada43f87a075c5
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
We should check PMU_BISR_STATUS register for
pd on/off status when bisr memory repair is
enabled.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Change-Id: If1d0927551ddea9757c70b3a948367132a83ed5c
Reads the extended DPRX caps (%DP_DP13_DPCD_REV) if present.
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: I5c442e4c92917e136665b3dd5554abef9b7c81e5
