The interleave is between power down and start of conversion,
This patch adds to workaround ic time sync issue for control.
Change-Id: Ib9f28fd92bcecf8ddaa8a69d47ced87fef04e7c6
Signed-off-by: Rocky Hao <rocky.hao@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
The RK3366 SoCs have two Temperature Sensors, channel 0 is for CPU
channel 1 is for GPU.
Change-Id: I71324c65e82804f52d464b986e1d86127f8dc040
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This helps to be absolutely sure of what CONFIG_* switches are enabled
for your build.
Change-Id: Ic1043d78b01502af9f5a2d4776672c66fc152f5c
Signed-off-by: Brian Norris <briannorris@chromium.org>
Reviewed-on: https://chrome-internal-review.googlesource.com/254936
Commit-Queue: Brian Norris <briannorris@google.com>
Tested-by: Brian Norris <briannorris@google.com>
Reviewed-by: Stephen Barber <smbarber@google.com>
Normally, the display regulator would be kept powered on by the
display/backlight driver, but we don't yet have a DT representation or
driver for this, as the PWM is controlled by the EC. Just force the
regulator on for now.
This wasn't needed on some boards yet, since they were forcing this
regulator "on." But for those where we might be controlling it, we need
this. (And it's harmless otherwise.)
This is necessary but not sufficient for getting UI up on my board.
Change-Id: I30650c178dd42d76542f8f2491e22d9bf548363e
Signed-off-by: Brian Norris <briannorris@chromium.org>
Reviewed-on: https://chrome-internal-review.googlesource.com/254935
Commit-Queue: Brian Norris <briannorris@google.com>
Tested-by: Brian Norris <briannorris@google.com>
Reviewed-by: Stephen Barber <smbarber@google.com>
Now, we can playback and capture via DA7219 machine driver call the
da7219_aad_jack_det (simple-card can not do this).
Change-Id: I8b1be189031f875b1c5328e9357115761a5f4da3
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
The DA7219 only support headphone playback, we may not call the
da7219_aad_jack_det when we use the simple-card.
Therefore, the machine driver may be need to submit upstream.
Change-Id: Iecf53fa62fcaf43175bbbcd2b7c8b0d5c67655ac
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
We recommend, VOP0 is the main screen, VOP1 is a sub screen,
only VOP0 is able to re-set parent (VPLL) rate.
Change-Id: If40f95ce18e73477df8f7f031013333a603d5eb2
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Because frac div need to more than 20 multiple between the numerator
and denominator, but we need to be fit many HDMI/DP freqs and may
bring serious jitter when the dclk_vopx below the dclk_vopx_frac.
Therefore, we can select dclk_vopx below the dclk_vopx_div directly.
Change-Id: If3d9051211f0b160a507f0942667796f043f4ec2
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
By default the device latches data on the falling edge of the
BCLK in DSP mode, whereas the expectation for normal BCLK is to
latch on the rising edge. This updates the driver to invert the
BCLK configuration for DSP mode, to align with expected behaviour.
Signed-off-by: Adam Thomson <Adam.Thomson.Opensource@diasemi.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit 4acfa36be6)
Change-Id: I646f6ec9fb377ce95d90d57c80dc05f13b6696f2
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Initial silicon did not have master bias enabled by default, unlike
later HW, so use regmap patch to align with newer defaults.
Signed-off-by: Adam Thomson <Adam.Thomson.Opensource@diasemi.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit abd7c894fc)
Change-Id: I1b941c779320b58110b78c2c127bb08629c7a3fa
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
PLL mode based on 32KHz master clock not supported in
AB silicon so remove support from the driver.
Signed-off-by: Adam Thomson <Adam.Thomson.Opensource@diasemi.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit 501f72e9c5)
Change-Id: Ie3e3388af33a74fca6bf60405e1b54b860b43f18
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
HW can provide 1.6V micbias level as well the existing levels
already provided in the driver. This patch adds support for 1.6V
to the DT binding.
Signed-off-by: Adam Thomson <Adam.Thomson.Opensource@diasemi.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit 0aed64c176)
Change-Id: I714fb76154242aa6392143ebe8db20a7510b45a3
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
In AB silicon, the internal LDO is not supported so remove
DT and driver references to this (digital voltage direct from
'VDD' supply)
Signed-off-by: Adam Thomson <Adam.Thomson.Opensource@diasemi.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit d8ef140dcc)
Change-Id: I540c28a7dd0994c5dd94889c2cc0f566f8fddb63
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
In current AB silicon, BIAS_EN field is enabled by default in the
REFERENCES register, so the regmap default value should reflect
this.
Signed-off-by: Adam Thomson <Adam.Thomson.Opensource@diasemi.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit 9ff0997904)
Change-Id: I8eabb89f669e02c6bda6ecee0b4253367082a59f
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
If codec probe() function fails after supplies have been enabled
it should really tidy up and disable them again. This patch updates
the probe function to do just that.
Signed-off-by: Adam Thomson <Adam.Thomson.Opensource@diasemi.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit 9069bf9bc8)
Change-Id: I3eebc1ff3af1b4f07fd564cc5d054ab0d6c43ad0
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Previously Sidetone would operate only when capture to DAI was in
progress, due to DAPM path configuration. There is no reason why
this should not operate without DAI capture, so this patch updates
the DAPM path accordingly.
Signed-off-by: Adam Thomson <Adam.Thomson.Opensource@diasemi.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit fdd50a8086)
Change-Id: I167dfe2bf18d696a01b8261b0fb0bb7a7569ec21
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit a737447d08)
Change-Id: I7b41ffe3d8144b1d4fa43dbf13e324f2f8d409ad
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
This patchset attempts to new compatible for thermal founding
on RK3366 SoCs.
Change-Id: Ida2a46f0c8dfb8f9e99c8c7ba488be07dac8a5e8
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Apparently the time constant for for the PWM regulator circuit on
gru-based devices is different than EVB. Let's run at 300kHz which
should make us work well.
BUG=None
TEST=None
Change-Id: I0973f416d026de27908c3ef527c1e9274b967fc8
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-on: https://chrome-internal-review.googlesource.com/254648
Reviewed-by: Stephen Barber <smbarber@google.com>
Tested-by: Doug Anderson <dianders@google.com>
There are 3 i2s sdio pins, which iomux mode is as follows:
- sdi3_sdo1
- sdi2_sdo2
- sdi1_sdo3
we need to configure these pins' iomux mode via the GRF register
when use multi channel playback/capture.
Change-Id: I95f01f425931d8fb826f33d5dad87ef8aa2b8b6e
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from git.kernel.org broonie/sound.git topic/rockchip
commit 72b7ba1f1477f1b9b0a3ddf2dd4b5392ce88a8a3)
Add functions to set force mode for host and device.
These functions will check the current mode and only
force if needed thus avoiding unnecessary force mode
delays. It's useful for dwc3 controller on some platforms
which don't support otg mode but support drd mode,
like rk3399 platform.
TEST=config dr_mode = "otg" in dts first, and do
"echo device > mode" on usb debugfs dir to force device mode,
do "echo host > mode" on usb debugfs dir to force host mode.
Change-Id: I1f90ac9d1ee3daa19c1046b0e52fdfb8f2d2ad62
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
The LG LP097QX1-SPA1 is an 9.7", 2048x1536 (QXGA) TFT-LCD panel
connected using eDP interfaces.
Change-Id: I3a279ff9e4dde421832e2f9fe8152ddfbadab2ae
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
The LG LP097QX1-SPA1 is an 9.7", 2048x1536 (QXGA) TFT-LCD panel
connected using eDP interfaces.
Change-Id: I09554d0c2afcce744e959878c7cd9d9950b35a17
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Replace the obsolete field ctrl_class with "which".
Make sure it not used in future modules by commenting out the field with
ifndef __KERNEL_ .
The field cannot be simply removed because that would be change on the
kenel API to the userspace (and we don't like that).
Change-Id: I21bfb7c2a4b553e74765213fd99c381d8b609cc0
Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
Signed-off-by: Alpha Lin <alpha.lin@rock-chips.com>
(cherry picked from commit 0f8017bebf)
So it can be used to get the default value of a control.
Without this change it is not possible to get the
default value of array controls.
Change-Id: I4370b7f2a40a08f28648f8dcaa3d84405db12523
Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
Signed-off-by: Alpha Lin <alpha.lin@rock-chips.com>
(cherry picked from commit 35ec2a2fa5)
The CONFIG_ANDROID_PARANOID_NETWORK will block network access on ChromeOS.
Disable it on CrOS.
CONFIG_DRM_DMA_SYNC can be used to synchronize CPU/GPU access to a buffer.
Change-Id: Ia979af42b8693161c854e1987122d49c8737b51c
Signed-off-by: ZhengShunQian <zhengsq@rock-chips.com>
These ioctls can be used to synchronize CPU/GPU access to a buffer.
BUG=chrome-os-partner:33438
TEST=add CONFIG_DRM_DMA_SYNC=y, in conjunction with xf86-video-armsoc change,\
run any X application, like xev
Change-Id: I8065ec465ebd0cb6abe128a3e7d92a8f74a88928
Signed-off-by: Dominik Behr <dbehr@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/229441
Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
Conflicts:
drivers/gpu/drm/rockchip/rockchip_drm_drv.c
drivers/gpu/drm/rockchip/rockchip_drm_drv.h
drivers/gpu/drm/rockchip/rockchip_drm_gem.c
(cherry picked from cros/chromeos-3.14 commit a847e1f492cbd186116c01a3f56575320dc87152)
Signed-off-by: ZhengShunQian <zhengsq@rock-chips.com>
Rockchip Socs have GPU, we need allocate GPU accelerated buffers.
So add special ioctls GEM_CREATE/GEM_MAP_OFFSET to support
accelerated buffers.
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
BUG=chromium:399935
TEST=With rest of patch set, can boot to UI on eDP
Change-Id: Ia4b13798aac97d16214da7a75a2479e6e334313e
Reviewed-on: https://chromium-review.googlesource.com/222153
Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
Tested-by: Daniel Kurtz <djkurtz@chromium.org>
Commit-Queue: Daniel Kurtz <djkurtz@chromium.org>
Conflicts:
drivers/gpu/drm/rockchip/rockchip_drm_drv.c
(cherry picked from cros/chromeos-3.14 commit c29c5a3037e18815937d8af664738e499ada94d1)
Signed-off-by: ZhengShunQian <zhengsq@rock-chips.com>
eDP controller need to declare which vop provide the video source,
and it's defined in GRF registers.
But the specific GRF register address is different between RK3288
and RK3399, so we need to create a device data to declare the GRF
messages for each CPU chips.
Change-Id: I695d1c729f5605d9e913c82453d311ed97c79a94
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
We hope to be able to HDMI/DP can obtain better signal quality,
therefore, we move VOP pwm and aclk clocks to other PLLs, let
HDMI/DP phyclock can monopolize VPLL.
Change-Id: Ib715f9d29c0743d113f9f74886ff3921c9e0a327
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
That's useful for every PWM controlled to adjust the voltage
regulators.
In the moment. We make savedefconfig to cleanup the rockchuip_cros_defconfig.
Change-Id: I33d68d6cd48310b2da0ea2c3331380e71fc51eee
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
This attempts to model commit 063e65397a ("ARM64: dts: rk3399-tb: fix
up the pwm regulator node").
Note that instead of putting a duty cycle of 25000 ns (40 kHz) I've set
a duty cycle of 1667 ns (600 kHz) because I think that's what the TRM
says.
Change-Id: Ifc209eddb20122feec96c5e86f7a14da7d74eb3f
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
We shouldn't need them in here if you are using the coreboot/firmware.
In general, the cmdline/memory/logic_center will be overwrited
since the coreboot will do that.
Change-Id: I3902ff4eb71891b5c6320bed4355992e699e4835
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
