This is workaround solution for IC design:
esmart can't support scale down when actual_w % 16 == 1.
Change-Id: I0fa090c5e28b79e644ef31ea1184b724b9d32ffa
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
According to test: Cluster can work with >, But
Esmart must enable gt2 when src_h = 2 * dst_h;
Change-Id: I3347eb4e340df093f7ab29afcb3a80ae5e03b0cc
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
post bcsh csc module need to know win overlay at yuv or rgb domain.
Change-Id: I246c22ddf0d02f48f515947a48ef058dca36c7a5
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Two sub windows in a cluster share same ctrl register bit.
Change-Id: I0a123fd3a1f63bbf0d6abea557e6024a99adb4cb
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
YUV 10 bit config value on Cluster is different
with Esmart/Smart.
Change-Id: If334f347b6d1759650113b36327a49a850f03e0e
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
When there is no layer attach to a port, the por_mux
should set to zero.
Change-Id: I880c3ff4ce8cac8ee41bdc7e6666d13796357cc6
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
If layer_sel or port_mux config done immediately, the layer
map and port mux may change when one frame is still in display
process.
Change-Id: I5611e75c56c89fd4fa02a069acc971c9266b05b6
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
This patch is from ARM via mail
"Fwd: 00209996 - [Rockchip][IMPORTANT] Cat A(rare)- Security bug in Mali DDK (16-Nov, 2020) Edit Subject"
Signed-off-by: Zhen Chen <chenzhen@rock-chips.com>
Change-Id: Ife807e5e850274222db8aea0e4cac588e02a8e53
In addition, rename some configs that have been used in drivers/gpu/arm/midgard.
Change-Id: I5356d6b3f544195eb6bebe88927abe7c8bcb7dd1
Signed-off-by: Zhen Chen <chenzhen@rock-chips.com>
Some platforms such as rk356x require more detailed configuration
partitioning to accommodate hdmi signal at different resolutions.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I4cc5fd4769ec51a5608b1901776d91f77324af3b
Change port_mux/layer_sel register as less as possible.
Change-Id: I7436cafcb9dd40ae9495091a08b0df479a79c978
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
A workaround to avoid display image shift on
screen when window enable.
Change-Id: I37064f580f7050997b521282d9cbae4193ace05d
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
the rb swap at crtc_atomic_enable can instead of uv swap, if RGB format
do rb swap and uv swap, the output data is still RGB, enable one of the
two function, the output data is BGR.
Change-Id: I6e929c2b9316e7ab691f159ba4dd792274a1dad5
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
before this commit, the bt1120/bt656/hdmi yuv output will display green
screen at power on state.
Change-Id: I21ee96f0883e0edc5f3a4cec1bf7bac25d15c775
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Only put pm_runtime when all crtc(video_port) disabled.
Change-Id: I38a41d8fda454081a5104ed5baea520a8498554a
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Use multiplication instead of division.
when gt4 enabled: src_h >>= 2;
when gt2 enable: src_h >>=1;
Change-Id: If47f873668f61b9a0690c665079bddfacc8429b5
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Fixes: d7ad116fb3 ("drm/rockchip: analogix_dp: Add support for rk3568")
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: I8cef87e13dd7c03baac730523c8f4b98d1a043f2
use actual pixel or dot clock in the hardware to calc the
timings and lane rate if dclk can not be applied accurately.
Change-Id: I6c0bcaca35cb945a58cc50005b23c6c772c9a082
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
