RK3568 has two USB 2.0 PHYs, and each PHY has two ports, the
OTG port of PHY0 support OTG mode with charging detection
function, they are similar to previous Rockchip SoCs.
However, there are three different designs for RK3568 USB 2.0 PHY.
1. RK3568 uses independent USB GRF module for each USB 2.0 PHY.
2. RK3568 accesses the registers of USB 2.0 PHY IP directly by APB.
3. The two ports of USB 2.0 PHY share one interrupt.
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: Id05718e25a20abdf9a4cb353b0fb94f0cb8b2d75
Add common helper function rockchip_usb2phy_port_irq_init() for
both otg port and host port to init their own irqs. It can help
to reduce redundant code, and also fix a issue that the id irq
isn't enabled for otg port if the vbus_always_on flag is true.
This patch introduces a combined irq for some inno usb2 phys
which combined the irqs of otg port and host port. We will used
it for RK3568 later.
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: Ifa74ec72e2b9d4ed62ee69e916b8ab2e8ae665b3
This patch implements a combo phy driver for Rockchip SoCs
with NaNeng IP block. This phy can be used as pcie-phy, usb3-phy,
sata-phy or sgmii-phy.
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: I86726e7eee643ea4cb3fadc56b0ee729903afc4f
This patch adds initial support for snps pcie 3.0
phy.
Change-Id: I23d0750a60ffde30f434e1c676916d4bc4772400
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
[ Upstream commit 05942b8c36 ]
The USB phy takes some time to reset, so make sure we give it to it. The
delay length was taken from the 4x12 phy driver.
This manifested in issues with the DWC2 driver since commit fe369e1826
("usb: dwc2: Make dwc2_readl/writel functions endianness-agnostic.")
where the endianness check would read the DWC ID as 0 due to the phy still
resetting, resulting in the wrong endian mode being chosen.
Signed-off-by: Jonathan Bakker <xc-racer2@live.ca>
Link: https://lore.kernel.org/r/BN6PR04MB06605D52502816E500683553A3D10@BN6PR04MB0660.namprd04.prod.outlook.com
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
commit afd55e6d1b upstream.
There were some problem in ipq8074 Gen2 PCIe phy init sequence.
1. Few register values were wrongly updated in the phy init sequence.
2. The register QSERDES_RX_SIGDET_CNTRL is a RX tuning parameter
register which is added in serdes table causing the wrong register
was getting updated.
3. Clocks and resets were not added in the phy init.
Fix these to make Gen2 PCIe port on ipq8074 devices to work.
Fixes: eef243d04b ("phy: qcom-qmp: Add support for IPQ8074")
Cc: stable@vger.kernel.org
Co-developed-by: Selvam Sathappan Periakaruppan <speriaka@codeaurora.org>
Signed-off-by: Selvam Sathappan Periakaruppan <speriaka@codeaurora.org>
Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org>
Link: https://lore.kernel.org/r/1596036607-11877-4-git-send-email-sivaprak@codeaurora.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
[ Upstream commit dcbabfeb17 ]
PHY calibration is needed only for USB2.0 (UTMI) PHY, so skip calling
calibration code when phy_calibrate() is called for USB3.0 (PIPE3) PHY.
Fixes: d8c80bb3b5 ("phy: exynos5-usbdrd: Calibrate LOS levels for exynos5420/5800")
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Link: https://lore.kernel.org/r/20200708133800.3336-1-m.szyprowski@samsung.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This patch add EXTCON_USB, EXTCON_USB_HOST and EXTCON_USB_VBUS_EN
to rockchip_usb_phy_extcon_cable. Without these extcons, the probe
of battery charger(such as rk818_charger) will fail when registering
extcon notifier.
Signed-off-by: Ren Jianing <jianing.ren@rock-chips.com>
Change-Id: I17774f63bc84fc1f5afa11d2ecc9d0eb2469acbc
[ Upstream commit 38b1927e5b ]
Currently pointer phy0 is being dereferenced via the assignment of
phy on the call to phy_get_drvdata before phy0 is null checked, this
can lead to a null pointer dereference. Fix this by performing the
null check on phy0 before the call to phy_get_drvdata. Also replace
the phy0 == NULL check with the more usual !phy0 idiom.
Addresses-Coverity: ("Dereference before null check")
Fixes: e6f32efb1b ("phy: sun4i-usb: Make sure to disable PHY0 passby for peripheral mode")
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Link: https://lore.kernel.org/r/20200625124428.83564-1-colin.king@canonical.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This patch can change phy internal 45 Ohm resistance accord to
reference resistance. The larger the reference resistance, the
greater the internal resistance, and accordingly, high speed
eye diagram amplitude will become lower.
The maximum adjustable range of the reference is +-20% of the
default value (200 Ohm).
Signed-off-by: Ren Jianing <jianing.ren@rock-chips.com>
Change-Id: Ibd746283c06609b944fa2a148066ba0a661e761a
The USB2.0 OTG PHY of RV1126/1109 which is designed for lower power
consumption provides only 8.8mA current source on DM. Multiplied
by 45 Ohm host termination resistance, voltage is about 400mV.
If the threshold voltage of host is greater than 400mV, the high
speed handshake will fail and SoC communicate at full speed. So
swing calibration is necessary.
We use gpio to control the 220 Ohm pull-up resistor to provide additional
current. Experiments show that the voltage of chirpK can be increases
to about 600mV.
Change-Id: I8b41054af4732569dbc8185bc3d3d4a2ba83cd6a
Signed-off-by: Jianing Ren <jianing.ren@rock-chips.com>
This reverts commit 955bb70bf1.
Fix the following changed report by build_abi.sh for GKI
'struct phy_ops at phy.h:56:1' changed:
type size changed from 512 to 576 (in bits)
1 data member insertion:
'int (phy*)* phy_ops::cp_test', at offset 448 (in bits) at phy.h:70:1
there are data member changes:
'module* phy_ops::owner' offset changed from 448 to 512 (in bits) (by +64 bits)
17 impacted interfaces
Change-Id: I5f163b804aaff2fe9c6e3a7c054de3f8df0c791c
Signed-off-by: William Wu <william.wu@rock-chips.com>
The rockchip_u3phy_cp_test() is used for USB3 compliance
test, and it depends on the cp_test of phy_ops which will
be dropped later, so we remove rockchip_u3phy_cp_test()
directly.
As a side effect, we need to use io commands to set the
USB3 enter compliance test mode instead of host_testmode
for RK3328 USB3 PHY.
Change-Id: Ie756b22f5bb89e146ad971f2668111a4733ff892
Signed-off-by: William Wu <william.wu@rock-chips.com>
The combphy_u3_cp_test() is used for USB3 compliance test,
and it depends on the cp_test of phy_ops which will be
dropped later, so we remove combphy_u3_cp_test directly.
As a side effect, we need to use io commands to set the
USB3 enter compliance test mode instead of host_testmode
for RK1808 USB3 combphy.
Change-Id: Iac7d9a4c6b0d2a74c284586f5dcbb48925691a91
Signed-off-by: William Wu <william.wu@rock-chips.com>
This patch will enable id interrupt for otg port when the property
vbus-always-on is set in dts.
If vbus is always on, bvalid interrupt won't make sense and be
disabled. But we cat change id state to switch drd mode by software.
Change-Id: I69fc3f00430dfd73835c6e99694d8d7c72c60c8c
Signed-off-by: Jianing Ren <jianing.ren@rock-chips.com>
By bypass charge detect module, about 140uA current can be saved
on USB_AVDD_1V8 power supply when suspend. Notice that bandgap
current can not be turned off, so there is still about 165uA
current.
This patch also remove the tuning in phy resuming, because the power
of phy is always on and registers does not need to be configured
again.
Change-Id: If13d3741e3b01289c1bd0294d6e6d88278c4654c
Signed-off-by: Jianing Ren <jianing.ren@rock-chips.com>
This patch remove the clks manegement in phy operations and keep the
clks always on. Keep the clks on can avoid many errors such as USB480M
clk abnormal output and EHCI controller error.
Change-Id: If201106d432d05e8fc5f63d595a67524e2183b5c
Signed-off-by: Jianing Ren <jianing.ren@rock-chips.com>
config bus-type in dts to distinguish between mipi and lvds.
bus-type = <3> for lvds interface.
Change-Id: I5c043bd238522768280e6e117c79476f27118c65
Signed-off-by: Cai YiWei <cyw@rock-chips.com>
Phy internal registers is read by APB bus. If you get phy registers
and APB data at the same time, you will get wrong data which is the
previous value of register. Therefore, pready_cnt must be set bigger
than rden_cnt.
Change-Id: I2e7e5544077170466bdaabc2f7d61f67a06b3283
Signed-off-by: Jianing Ren <jianing.ren@rock-chips.com>
This allows adding fields to clk_init_data without having to explicitly
set those fields in all the drivers.
Fixes: 2071154513 ("ANDROID: GKI: clk: Initialize in stack clk_init_data to 0 in all drivers")
Change-Id: I4593151b2624d2ccfaf477d36ff1f4d331f2ca91
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
This allows adding fields to clk_init_data without having to explicitly
set those fields in all the drivers.
Fixes: 2071154513 ("ANDROID: GKI: clk: Initialize in stack clk_init_data to 0 in all drivers")
Change-Id: If1fb768aadc89025cccc131441c3aa32045ba382
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
This allows adding fields to clk_init_data without having to explicitly
set those fields in all the drivers.
Fixes: 2071154513 ("ANDROID: GKI: clk: Initialize in stack clk_init_data to 0 in all drivers")
Change-Id: I6d958aa57097209165cf32a671f9612752eec4f1
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
This allows adding fields to clk_init_data without having to explicitly
set those fields in all the drivers.
Fixes: 2071154513 ("ANDROID: GKI: clk: Initialize in stack clk_init_data to 0 in all drivers")
Change-Id: I382ee237c596e79e29bf6c4b13a4dc6c0c94344f
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
This allows adding fields to clk_init_data without having to explicitly
set those fields in all the drivers.
Fixes: 2071154513 ("ANDROID: GKI: clk: Initialize in stack clk_init_data to 0 in all drivers")
Change-Id: Ibe59e24929f89e6124ee0c74195515421625f386
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
This allows adding fields to clk_init_data without having to explicitly
set those fields in all the drivers.
Fixes: 2071154513 ("ANDROID: GKI: clk: Initialize in stack clk_init_data to 0 in all drivers")
Change-Id: I4fd81155cfbd6c257d3a52eda25714e07a4e6abb
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
According to the Naneng Specifation, opmode should be set
to 2b'01 Non-driving mode when suspend.
Change-Id: Ib43ef64af2e7fc413125f68ebeb72743f23e0050
Signed-off-by: Jianing Ren <jianing.ren@rock-chips.com>
This patch implements a usb 2.0 phy driver for Rockchip SoCs with
Naneng IP block.
Change-Id: I2658ce7c77a4bef60c8ab183a687d81468a512f1
Signed-off-by: Jianing Ren <jianing.ren@rock-chips.com>
add mutex for mipidphy_s_stream to fix n4 green issue
Signed-off-by: Wang Panzhenzhuan <randy.wang@rock-chips.com>
Change-Id: I7fe7a5b0369569757e3f3c179e37bb4f5e8967ce
Innosilicon LVDS/TTL PHY implements LVDS TIA/EIA protocol.
Normally, Innosilicon LVDS/TTL PHY contains four 7-bit
parallel-load serial-out shift registers, a 7X clock PLL,
and five Low-Voltage Differential Signaling (LVDS) line drivers
in a single integrated circuit. These functions allow 28 bits
of single-ended LVTTL data to be synchronously transmitted over
five balanced-pair conductors for receipt by a compatible receiver.
In addition, Innosilicon LVDS/TTL PHY could extend from 4 lanes
to N lanes (N is required by the customer). Therefore, the TTL
lines extend respectively.
Change-Id: Ib48537c49dec919e2ed5bc6347217fe83be07371
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
commit 46b7edf1c7 upstream.
I've noticed that when writing data to the modem the writes can time out
at some point eventually. Looks like kicking the modem idle GPIO every
600 ms instead of once a second fixes the issue. Note that this rate is
different from our runtime PM autosuspend rate MDM6600_MODEM_IDLE_DELAY_MS
that we still want to keep at 1 second, so let's add a separate define for
PHY_MDM6600_IDLE_KICK_MS.
Fixes: f7f50b2a7b ("phy: mapphone-mdm6600: Add runtime PM support for n_gsm on USB suspend")
Cc: Marcel Partap <mpartap@gmx.net>
Cc: Merlijn Wajer <merlijn@wizzup.org>
Cc: Michael Scott <hashcode0f@gmail.com>
Cc: NeKit <nekit1000@gmail.com>
Cc: Pavel Machek <pavel@ucw.cz>
Cc: Sebastian Reichel <sre@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
commit be4e3c737e upstream.
We have an interrupt handler for the wake-up GPIO pin, but we're missing
the code to wake-up the system. This can cause timeouts receiving data
for the UART that shares the wake-up GPIO pin with the USB PHY.
All we need to do is just wake the system and kick the autosuspend
timeout to fix the issue.
Fixes: 5d1ebbda03 ("phy: mapphone-mdm6600: Add USB PHY driver for MDM6600 on Droid 4")
Cc: Marcel Partap <mpartap@gmx.net>
Cc: Merlijn Wajer <merlijn@wizzup.org>
Cc: Michael Scott <hashcode0f@gmail.com>
Cc: NeKit <nekit1000@gmail.com>
Cc: Pavel Machek <pavel@ucw.cz>
Cc: Sebastian Reichel <sre@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
The INNO MIPI D-PHY is built in witch a standard digital interface
to talk to any third part Host controller.That is part of Rockchip SoCs,
like rk3368.
Change-Id: I9806882e0e3fb6b20348015d0f34923d1bc46b89
Signed-off-by: WeiYong Bi <bivvy.bi@rock-chips.com>
Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
Add eDP PHY support for RK3368 SoC. RK3368 eDP PHY is similar to
the RK3288.
Change-Id: Ic2134ba719dadba121dc2fcc944662ef06b2ecfa
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
