Calling the complete callback when a request is cancelled leads to
locking problems in the callback, which could be called from an IRQ
with no locks held, or from whatever context called
tegra_dma_dequeue_req. Instead, expect the caller to handle the
now-cancelled request as needed.
Also removes tegra_dma_dequeue, since all users can be trivially
converted to tegra_dma_dequeue_req.
Change-Id: If699239c09c78d1cd3afa0eaad46535b1d401a24
Signed-off-by: Colin Cross <ccross@android.com>
Update tegra_init_emc to provide generic memory
vendor matching. Read values from EMC_MRR_0, to
uniquely identify memory types and compare them
to table of memory passed in.
Change-Id: Ie116fa6f497076149c87ff6c0ae0621309bac65f
Signed-off-by: James Wylder <james.wylder@motorola.com>
tegra_assert_system_reset is called after the cache is disabled.
Calling writel will cause the PL310 store buffers to be drained,
which requires taking a spinlock. Taking a spinlock is not safe
after the caches are disabled. Convert to readl_relaxed and
writel_relaxed.
Change-Id: I6850179b931ca865580c0fd3fe003b46bdfa43ae
Signed-off-by: Colin Cross <ccross@android.com>
The kernel now receives wait tracking data (similar to gathers and
relocs) and compares the current syncpt with the threshold value.
If it's old, it gets a kernel mapping and rewrites the method data
to use a kernel reserved syncpt that is always 0 (so trivially pops
when seen by the HW).
Patch has dependency to the user-space patches
Submitted on behalf of: Chris Johnson <cjohnson@nvidia.com>
original work by: Chris Johnson <cjohnson@nvidia.com>
Change-Id: I4d4e5d3b49cab860485c4172f87247f5b4f5ea6e
get_spare_fuse was calling tegra_apb_readl and passing an
offset, but tegra_apb_readl requires a physical address.
Fix it by calling tegra_fuse_readl instead, which takes
an offset.
Fixes a crash booting on A03 parts, where get_spare_fuse
is used to determine the difference between A03 and A03
prime.
Change-Id: Ie386dc099e1c14eeb36262bfcc882e29a40a8da6
Signed-off-by: Colin Cross <ccross@android.com>
Change-Id: I165411a14342666cbac02fb8cb171580ab0826aa
Reviewed-on: http://git-master/r/14464
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
Tested-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Signed-off-by: Jon Mayo <jmayo@nvidia.com>
Change-Id: I89fc144428b140288126790065902ea9e49b41e4
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
Tested-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Signed-off-by: Jon Mayo <jmayo@nvidia.com>
Change-Id: I7e8d9b5fa275af738fe22be2082a709a3902bdee
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
Tested-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Signed-off-by: Jon Mayo <jmayo@nvidia.com>
factory programmed encrypted key fuses held in kfuse module.
use APB DMA for accessing kfuse registers, reading directly can hang if any
other DMA is active.
Change-Id: I85e44cc169607bc22116075e28938014aa299d75
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
Tested-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Signed-off-by: Jon Mayo <jmayo@nvidia.com>
Device /dev/nvhdcpX is used to manage NVHDCP on framebuffer /dev/fbX.
These devices are created on hdmi driver initialition when it is
attached to dc. Currently only one nvhdcp device may be created. An ioctl
interface is in video/nvhdcp.h
Check for repeaters and store repeater info. userspace application
queries this status to authenticate the connection. When authentication
fails, auto-renegotiate every 1.75 seconds. Give up after 5 failed attempts,
reset after hotplug or policy change.
use TEGRA_DC_OUT_NVHDCP_POLICY_ON_DEMAND in tegra_dc_out.flags in board
panel configuration to select a different default policy at probe. Currently
only TEGRA_DC_OUT_NVHDCP_POLICY_ALWAYS_ON is supported.
Change-Id: I0db66fc86096b98d2604544061721d291523de75
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
Tested-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-by: Phillip Smith <psmith@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Signed-off-by: Erik Gilling <konkers@android.com>
Tegra 2.6.36 code needs to restore PL310 dynamic clock gating upon
resume from a power event.
As of 2.6.39 the PL310 is re-init'ed from scratch upon resume,
and this patch can be dropped.
Change-Id: I8c1fb1add3c3cfcffff58fab642b84d8d5a7a90a
Signed-off-by: Todd Poynor <toddpoynor@google.com>
Enable dynamic high level clock gating for Cortex-A9 CPUs, as
described in 2.3.3 "Dynamic high level clock gating" of the
Cortex-A9 TRM. This may cut the clock of the integer core,
system control block, and Data Engine in certain conditions.
Add ARM errata 720791 to avoid corrupting the Jazelle
instruction stream on earlier Cortex-A9 revisions.
Change-Id: I48e51d907e593f26982ea91b0a811553f68e3c86
Signed-off-by: Todd Poynor <toddpoynor@google.com>
The cache controller will stop its clock when idle after several
clock cycles.
Change-Id: Ifc9997d4e7fd4f1e3c6129bac2fd42f8995a069e
Signed-off-by: Todd Poynor <toddpoynor@google.com>
Enable data prefetching in the L2 cache controller, and set
the prefetch offset to 7.
Memcpy performance measured copying 16 MB buffers 78 times:
Data prefetch disabled, prefetch offset 0: 440 MB/s
Enabling data prefetching, prefetch offset 0: 430 MB/s
Enabling data prefetching, prefetch offset 7: 502 MB/s
Overall, this patch gives a 14% improvement in memcpy performance.
Prefetch offset of 8 causes prefetches to cross 4k boundaries
and cannot be used.
Original-author: Gary King <gking@nvidia.com>
Signed-off-by: Chris Fries <C.Fries@motorola.com>
Signed-off-by: Colin Cross <ccross@android.com>
Change-Id: I7ce0810b3f94edc2640df3f643cf81357052f2f1
Timer ticks aren't properly serviced while a CPU is in LP2 idle.
Although the Tegra LP2 idle code calls hrtimer_peek_ahead_timers,
because no IRQ regs have been saved, update_process_times is not
called, and thus the timer list is not serviced (and neither is
SMP rebalancing, etc.) This can cause significant delays
scheduling timer-based activity, especially on CPU 1 (which is
not servicing most other IRQs).
Colin Cross suggested a patch based on upstream review feedback
that uses clock notifiers to switch to the "broadcast" clock event
source ("timer0" Tegra timer 3) during LP2, which has a real
interrupt handler defined that calls the clock event handler in
IRQ context, allowing timers to be checked.
Change-Id: Ifa3f4ec662f07dc9636e433f278358f75b65d10c
Signed-off-by: Todd Poynor <toddpoynor@google.com>
If the PC on the stack is updated in entry-armv.S,
do_undefinstr can get called after the fixup. do_undefinstr
does its own fixup, and doing both causes the PC to point to
half way through an instruction.
Instead, do the fixup in do_vfp, where only the vfp code
can get called.
Change-Id: I6d966887adc8ed58d88bfe0cb3c0ba29213be488
Signed-off-by: Colin Cross <ccross@android.com>
Fixed a problem preventing independent setup/teardown
of TX and RX DMAs when setting playback or capture buffer count.
Signed-off-by: Eric Laurent <elaurent@google.com>
instead of fused value. This is required
to meet High Speed USB signaling requirements.
Change-Id: I659b33faa950605ecf040598112e1972047ae7ad
Signed-off-by: Nathan Connell <w14185@motorola.com>
