The operation of reading back flash cache after programing is not
universal. At present, only ESMT devices are found to have this anomaly.
Change-Id: I3ec21eebc4aa7b8a259129ed2c036e1168553f27
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
1.max_dll_cells is 0x1FF when sfc_ver_4
2.sfc_set_delay_lines to zero means disable dll
3.bypass dll training when there is no device
4.Adjust the dll_value to from the middle of the dll window to
the better one
5.Change RKSFC_DLL_THRESHOLD_RATE to ">50MHz"
Change-Id: Ibd669420899925272c74e190fee8c62c09db8d14
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
When the related print appears, it means that the SDK is too old
and the storage driver needs to be updated.
Change-Id: I63f45fba4cf52108c628f225ee23aa0819ca256f
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
When internal DMA ready, the last spare data may still in fifo.
Change-Id: I1cf670d2008ea62b67b517641e31386fd0877417
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
The nandc's DMA only supports 32bits. When the DDR capacity exceeds 4GB,
It need to configure DMA mask to 32bits and use API dma_map_single to
get the physical address.
Change-Id: I1510f7bbe2779ea20ff83a93e3a4dabb941263e3
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
According to commit b350bee5e, use SYNC_SKCIPHER_REQUEST_ON_STACK
Change-Id: I2f81640b39e2f9b9d38534dfe633196158dff89b
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
1.Support after SFC ver 4
2.If the io rate is high than 100MHz, enable SFC delay line in
default
3.Get id byte as data pattern
Change-Id: Ia405771c0bc94eddaa45e1d85c7fa10a85c40531
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Part of spinand sram maybe change after read status register
Fixes: cf69491c97 ("drivers: rkflash: Add spinand program cache recheck")
Change-Id: Ia8f902fe51562d71a5b8e78a80e63eb26257df38
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Add spinand power lost situation protection to avoid
abnormal data written to flash array(recheck 1) or
just reduce error behavior(recheck 2)
Change-Id: Ic445fd09fd407c225b47310d666b39f095fcfb17
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
In file included from drivers/rkflash/sfc_nand_mtd.c:6:0:
./include/linux/mtd/cfi.h:76:2: warning: #warning No CONFIG_MTD_CFI_Ix selected. No NOR chip support can work. [-Wcpp]
error, forbidden warning:cfi.h:76
#warning No CONFIG_MTD_CFI_Ix selected. No NOR chip support can work.
^~~~~~~
scripts/Makefile.build:333: recipe for target 'drivers/rkflash/sfc_nand_mtd.o' failed
make[2]: *** [drivers/rkflash/sfc_nand_mtd.o] Error 1
make[2]: *** Waiting for unfinished jobs....
In file included from drivers/rkflash/sfc_nor_mtd.c:6:0:
./include/linux/mtd/cfi.h:76:2: warning: #warning No CONFIG_MTD_CFI_Ix selected. No NOR chip support can work. [-Wcpp]
error, forbidden warning:cfi.h:76
Change-Id: I900d20adbd86c8293a9496ffba4bd722a46bfeae
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
1.Change to use RK MTD vendor operation
2.RK MTD vendor is incompatible with RK vendor
Change-Id: I7c233b0b0a98c5e93d0722956809a9d6c01663a1
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Fixes: 008340a82 ("drivers: rkflash: Change to use the api which the oob area available")
Change-Id: I140aa76a2acb73271ba04b7060030dc06a2353e6
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Fixes: 69f3c341d9 ("drivers: rkflash: Support spinand non aligned read")
Change-Id: I3146cd574ac77c2d1a0b5b6563440d86766a0a9a
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
1.Add more information for SPI Nand MTD debug
2.Return program result
Change-Id: I3fc7d63955355ad88adfbd02f0b67fc16c9d76d5
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
