This adds typec orientation switch to support the TCPM framework
for Type-C feature.
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Change-Id: I14aa2bc6a4a377733bd5bfd1e2ff77820dbc2758
When HDMI0/1 are bound to the same VP, vop will only set one dclk rate,
The frequency of another dclk will not be changed. But HDMI driver will
set phy output frequency, The dclk core->rate does not correspond to the
actual phy output frequency. So dclk core->rate need to be updated when
enable dclk.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I497bf9a01b8210c17b1c720839fc8f5d15dd0baf
Phy must be reset or GRF_HDPTX_STATUS will always show phy
is locked.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I9f1ade5ce6f744b1d9590f72b95bc18c58b6d12b
RV1103 doesn't have VBUSDET pin for the usb phy to
detect the USB VBUS, and the default status of bvalid
is inactive(low level), it cause the dwc3 controller
fail to start usb device connection, so it needs to
set bvalid to high by grf for RV1103.
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: If63c68270c14ff8fa402805a33ce3061f6f796ab
When build with rv1106_defconfig, and enable the following
configs manually:
CONFIG_EXTCON=y
CONFIG_USB_SUPPORT=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
size drivers/phy/rockchip/phy-rockchip-inno-usb2.o
before:
text data bss dec hex filename
65118 204 4 65326 ff2e drivers/phy/rockchip/phy-rockchip-inno-usb2.o
after:
text data bss dec hex filename
13780 204 4 13988 36a4 drivers/phy/rockchip/phy-rockchip-inno-usb2.o
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: Ia8900c17800a4ae9ae04e91f46d71986eda242c0
take 1280x720@60Hz which pclk is 74.25Mhz as an example, the dsi
lane rate should set 445500 Kbps/lane(pclk x bpp = lane_rate x lanes)
when mipi work in no video burst pulse/event, therefore the PLL should
output the rate of Kbps/ksps level for normal display.
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
Change-Id: I63bf5717e2da521b7af18d88c906b86e30a71488
If set dclk to the same frequency as before, the set_rate callback
won't be called. Hdmi phy is not configured correctly. So hdmi phy
must be configured in the clk enable callback.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: Ie780a5969b342595fa94c60dd58889b9bf2bb78b
The vogrf register is cleared when system suspend. It need
config the hpd status when system resume.
Change-Id: I50419b8496ba389193238cae08e3710172f6c5be
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
usleep shouldn't be used in an atomic context.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I9c6accd1b17488f4ad25b79681856c47fab29d20
When DP show the uboot logo, the usbdp phy will work in uboot.
In this case, the display on DP will be broken if we initialize
the usbdp phy again when system enter kernel.
Reading the lane mux and enable register when probe the usbdp
phy driver. If DP used the usbdp phy in uboot, It should skip
the initialization.
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: I55dcf8bd9c0b8be94326dd17c53ad47237cd1975
This patch adds phy configuration for rv1106 usb2 phy
which has only one otg port.
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: Ida93914f3eae3d692265bcf9751d9150619098af
HDMI PHY PLL adds 154M and 119M support, while fixing 146.25M
and 85.5M parameters
Signed-off-by: Lei Chen <lei.chen@rock-chips.com>
Change-Id: I12465d6c025737b80761d83687ec4d93d18b1c51
For support kernel logo, don't disable phy when phy probe.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I04168e1374104480c1fa611539938f1374967bd7
Interface functions may call by different threads, which may
access the same value at the same time. So we need add mutex
lock.
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: I682820c0eb366d514e21cc54f9ab97d5039a0814
According to the result of SI test, adjust the ssc, voltage
swing, pre-emphasis to improve the phy compatibility.
Different rates use different parameters. The rbr and hbr
use the same parameters. Note that Type-C port's parameters
and DP standard port's parameters are different when the
lane rate is rbr or hbr.
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: I27a8a846a198c7feabf1aaf1459a7df056e4312a
RK3588 has two OTG controllers, OTG0 is configured as
OTG mode, and OTG1 is configured as host mode. The OTG1
doesn't init the otg sm work, so it can only handle the
otg sm work if the func of the work is initialized.
This patch can fix the warning if the logic is power off
during deep sleep on RK3588 EVB2.
WARNING: CPU: 0 PID: 145 at kernel/workqueue.c:3057 __flush_work+0x26c/0x28c
Modules linked in:
CPU: 0 PID: 145 Comm: irq/106-rockchi Not tainted 5.10.66 #720
Hardware name: Rockchip RK3588 EVB2 LP4 V10 Board (DT)
pstate: 60c00009 (nZCv daif +PAN +UAO -TCO BTYPE=--)
pc : __flush_work+0x26c/0x28c
lr : __cancel_work_timer+0x11c/0x1c0
......
Call trace:
__flush_work+0x26c/0x28c
__cancel_work_timer+0x11c/0x1c0
cancel_delayed_work_sync+0x18/0x2c
rockchip_usb2phy_bvalid_irq+0xf4/0x144
rockchip_usb2phy_irq+0x368/0x384
irq_thread_fn+0x34/0x88
irq_thread+0x1a4/0x248
kthread+0x13c/0x344
ret_from_fork+0x10/0x30
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: I42b5f6d22df3f7f94d54f05083694fb49e382620
If phy pll is used, we don't power off phy. Delay to do
the phy power off work when the phy pll isn't used.
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: I5a90bc7de2664da2775a81e89aedc26c42da7062
HDMI phy pll Ksub can't set to 0, or some frequencies may
have slight deviation.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I5e9b6faf7a4397b2b43beea7094fbd3f4b4cb46b
The RK3588 usb3 otg controller connected with one usb2 phy
and one usb3 phy. The usb2 phy used UTMI+ interface, and
the usb3 phy used PIPE interface. The usb3 otg controller
initialization depends on the pipe phystatus which from
usb3 phy by default. If the usb3 phy is disabled, it needs
to select the pipe phystatus from usb grf with the property
"rockchip,sel-pipe-phystatus".
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: I5015a18a19c14ccb43530fbae15200c8cb3ab242
The usb2-phy driver needs to know the plug-in and plug-out information
from TCPM (Type-C Port Manager) for USB2.0 Type-C scheme, so adds the
orientation switch support in usb2-phy driver, and the corresponding
DT nodes is required, please refer to the following example.
[...]
&u2phy0 {
orientation-switch;
port {
#address-cells = <1>;
#size-cells = <0>;
u2phy0_orientation_switch: endpoint@0 {
reg = <0>;
remote-endpoint = <&usbc0_orien_sw>;
};
};
};
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: I51ca0999dcecaf4aa9f21be453dce2fddb6f9c9f
For Type-C interface with PD chip (e.g FUSB302), the vbus-det
pin is always pulled up. So the A-valid and B-valid registers
art not change in this case, however, we still want to check
the usb hotplug in otg_sm_work, so let's check the vbus valid
software control registers which are set in typec_switch ops
(e.g udphy_orien_sw_set() on RK3588 Type-C).
Furthermore, schedule the otg_sm_work immediately after phy
init for charger detection before usb enumeration.
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: I00d2e3e1094e35e9cb34632a9607b372d593e62a
Registering orien switch only when "orientation-switch" property
is configured in DT.
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Change-Id: Ic2701911583d8ad047d596c3c91ba32b56d62fff
This patch sets iddig_en to 1 for RK3588 USB3_0 and
USB3_1 by default, then it can handle the id irq in
rockchip_usb2phy_irq() if the mode is USB_DR_MODE_HOST
when the PD_BUS is power off.
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: Ifee1155c72eead4d9faf74b7808c4dd2f6f719eb
This patch aims to reduce the power consumptiom of usb2 phys
for rk3588. For lowest power consumption, we set the phy1/2/3
enter IDDQ mode by default in uboot spl stage.
IDDQ mode power consumption:
AVCC_1V8_S0 : 0.2mA (0.05mA per phy)
AVDD_0V75_S0: 0.2mA (0.05mA per phy)
VCC_3V3_S0 : 0.2mA (0.05mA per phy)
In kernel, we needs to set the phy exit from IDDQ mode and
reset the phy to enter normal mode firstly. We use suspend
mode instead of IDDQ mode for dynamic power management,
because IDDQ mode will power down all analog blocks and that
cause the usb controllers working abnormally.
Suspend mode power consumption:
AVCC_1V8_S0 : 12.5mA (3.125mA per phy)
AVDD_0V75_S0: 10.3mA (2.575mA per phy)
VCC_3V3_S0 : 0.2mA (0.050mA per phy)
For Type-C0 USB OTG mode, set phy suspend control from GRF,
it can help to reduce the suspend power consumption:
AVCC_1V8_S0 : reduce 5.1mA
AVDD_0V75_S0 : reduce 4.6mA
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: I610b95f9bb6da38d25ed2e78b0a87dcb4db8cc38
Should use REG_19H instead of REG_DH.
Fixes: e6ae079436 ("phy: rockchip: naneng-combphy: Force detect Rx for RK356X and RK3588 SoCs")
Change-Id: Ifc9484e850955e6a36c30755a7ba1aee65070d0f
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
When usb dp phy config as USB + DP mode, the phy clk is work
and the dp lane is enabled by initial action, whether the dp
function need work or not. In the case only usb function
work, which will consume more power.
To improve this issue, we release the dp phy pll reset and
enable the dp lane when dp power on.
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: I678edc130ddef07f85b007577089a9689e12e2d4
https://source.android.com/security/bulletin/2021-12-01
CVE-2021-33909
CVE-2021-38204
CVE-2021-0961
* tag 'ASB-2021-12-05_12-5.10': (3010 commits)
ANDROID: workqueue: export symbol of the function wq_worker_comm()
ANDROID: GKI: Update symbols to symbol list
ANDROID: vendor_hooks: Add hooks for binder proc transaction
ANDROID: GKI: Add symbols abi for USB IP kernel modules.
ANDROID: GKI: Fix file mode on mtk abi file
UPSTREAM: erofs: fix deadlock when shrink erofs slab
ANDROID: init_task: Init android vendor and oem data
UPSTREAM: sched/core: Mitigate race cpus_share_cache()/update_top_cache_domain()
ANDROID: Update symbol list for mtk
UPSTREAM: erofs: fix unsafe pagevec reuse of hooked pclusters
UPSTREAM: erofs: remove the occupied parameter from z_erofs_pagevec_enqueue()
UPSTREAM: usb: dwc3: gadget: Fix null pointer exception
ANDROID: fips140: support "evaluation testing" builds via build.sh
FROMGIT: sched/scs: Reset task stack state in bringup_cpu()
ANDROID: dma-buf: heaps: fix dma-buf heap pool pages stat
ANDROID: ABI: Add several spi_mem related symbols
UPSTREAM: spi: spi-mem: add spi_mem_dtr_supports_op()
ANDROID: gki_defconfig: enable CONFIG_SPI_MEM
ANDROID: ABI: Add several iio related symbols
ANDROID: ABI: Update symbol list for IMX
...
Change-Id: I09cddc92fa34553b944e62cc5cbbba94a84e5437
Conflicts:
arch/arm/boot/dts/rk322x.dtsi
arch/arm64/boot/dts/rockchip/rk3399.dtsi
drivers/dma-buf/heaps/system_heap.c
drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
drivers/gpu/drm/rockchip/rockchip_drm_vop.c
drivers/gpu/drm/rockchip/rockchip_lvds.c
drivers/gpu/drm/rockchip/rockchip_vop_reg.c
drivers/mtd/nand/spi/core.c
drivers/pci/controller/pcie-rockchip-host.c
drivers/soc/rockchip/Kconfig
drivers/usb/dwc3/core.c
drivers/usb/dwc3/core.h
