Adding FLAG "SPINAND_HAS_QE_BIT" for Quad mode support on Macronix
Serial Flash.
Validated via normal(default) and QUAD mode by read, erase, read back,
on Xilinx Zynq PicoZed FPGA board which included Macronix
SPI Host(drivers/spi/spi-mxic.c).
Change-Id: I7951dd4705cdc7e03bd697da33d216cfd5237b4c
Signed-off-by: Jaime Liao <jaimeliao@mxic.com.tw>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/1628472472-32008-1-git-send-email-jaimeliao@mxic.com.tw
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 6f802696c2)
https://source.android.com/security/bulletin/2021-12-01
CVE-2021-33909
CVE-2021-38204
CVE-2021-0961
* tag 'ASB-2021-12-05_12-5.10': (3010 commits)
ANDROID: workqueue: export symbol of the function wq_worker_comm()
ANDROID: GKI: Update symbols to symbol list
ANDROID: vendor_hooks: Add hooks for binder proc transaction
ANDROID: GKI: Add symbols abi for USB IP kernel modules.
ANDROID: GKI: Fix file mode on mtk abi file
UPSTREAM: erofs: fix deadlock when shrink erofs slab
ANDROID: init_task: Init android vendor and oem data
UPSTREAM: sched/core: Mitigate race cpus_share_cache()/update_top_cache_domain()
ANDROID: Update symbol list for mtk
UPSTREAM: erofs: fix unsafe pagevec reuse of hooked pclusters
UPSTREAM: erofs: remove the occupied parameter from z_erofs_pagevec_enqueue()
UPSTREAM: usb: dwc3: gadget: Fix null pointer exception
ANDROID: fips140: support "evaluation testing" builds via build.sh
FROMGIT: sched/scs: Reset task stack state in bringup_cpu()
ANDROID: dma-buf: heaps: fix dma-buf heap pool pages stat
ANDROID: ABI: Add several spi_mem related symbols
UPSTREAM: spi: spi-mem: add spi_mem_dtr_supports_op()
ANDROID: gki_defconfig: enable CONFIG_SPI_MEM
ANDROID: ABI: Add several iio related symbols
ANDROID: ABI: Update symbol list for IMX
...
Change-Id: I09cddc92fa34553b944e62cc5cbbba94a84e5437
Conflicts:
arch/arm/boot/dts/rk322x.dtsi
arch/arm64/boot/dts/rockchip/rk3399.dtsi
drivers/dma-buf/heaps/system_heap.c
drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
drivers/gpu/drm/rockchip/rockchip_drm_vop.c
drivers/gpu/drm/rockchip/rockchip_lvds.c
drivers/gpu/drm/rockchip/rockchip_vop_reg.c
drivers/mtd/nand/spi/core.c
drivers/pci/controller/pcie-rockchip-host.c
drivers/soc/rockchip/Kconfig
drivers/usb/dwc3/core.c
drivers/usb/dwc3/core.h
FS35ND01G-S1Y2, FS35ND02G-S3Y2, FS35ND04G-S2Y2, fsxxndxxg
Change-Id: Icdff45a209b5aa4dd2827e0e58bd543a84f9d809
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Spinand may power off after suspending, so the corresponding resume
process is necessary.
Change-Id: I36c7dbf23877b342dfe9e7fb0c8eb4885bd46d71
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
According to macronix website, there is no mx66l51235l part number.
The chip detected as such is actually mx66l51235f. Rename the flash.
Do not update the mx66l51235l name from the spi_nor_dev_ids[], since
there are dt that are using this compatible.
Change-Id: I23594ca8301572df8024b413379e1d688f8ca793
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit d406f49b05)
Add support for w25q512jvq. This is of the same series chip with
w25q256jv, which is already supported, but with size doubled and
different JEDEC ID.
Tested on Intel whitley platform with dd from/to the flash for
read/write respectly, and flash_erase for erasing the flash.
Change-Id: I3b4243a0391ae994af131062a8a21f659494fccb
Signed-off-by: Shuhao Mai <shuhao.mai.1990@gmail.com>
[ta: put flash_info flags in order, first SPI_NOR_DUAL_READ, then
SPI_NOR_QUAD_READ]
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Link: https://lore.kernel.org/r/20210208075303.4200-1-shuhao.mai.1990@gmail.com
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit ff013330fb)
The relevant changes to the already existing GD5F1GQ4UExxG support has
been determined by consulting the GigaDevice product change notice
AN-0392-10, version 1.0 from November 30, 2020.
As the overlaps are huge, variable names have been generalized
accordingly.
Apart from the lowered ECC strength (4 instead of 8 bits per 512 bytes),
the new device ID, and the extra quad IO dummy byte, no changes had to
be taken into account.
New hardware features are not supported, namely:
- Power on reset
- Unique ID
- Double transfer rate (DTR)
- Parameter page
- Random data quad IO
The inverted semantic of the "driver strength" register bits, defaulting
to 100% instead of 50% for the Q5 devices, got ignored as the driver has
never touched them anyway.
The no longer supported "read from cache during block erase"
functionality is not reflected as the current SPI NAND core does not
support it anyway.
Implementation has been tested on MediaTek MT7688 based GARDENA smart
Gateways using both, GigaDevice GD5F1GQ5UEYIG and GD5F1GQ4UBYIG.
Change-Id: I0e819a07711e58542af2bcf753b4ecb10eb9f882
Signed-off-by: Reto Schneider <reto.schneider@husqvarnagroup.com>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/20210211113619.3502-1-code@reto-schneider.ch
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 469b992489)
The MT29F2G01AAAED is a single die, 2Gb Micron SPI NAND Flash with 4-bit
ECC
Change-Id: I6b1baaef7e092bf932a8fdbcb66d3db2e36ef900
Signed-off-by: Thirumalesha Narasimhappa <nthirumalesha7@gmail.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/20201108113735.2533-3-nthirumalesha7@gmail.com
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 8c573d9419)
Rename the read/write/update of SPINAND_OP_VARIANTS() to more
specialized names.
Change-Id: I5c02b9bf76376ea4ed320cf49be1f7630329dfc3
Signed-off-by: Thirumalesha Narasimhappa <nthirumalesha7@gmail.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/20201108113735.2533-2-nthirumalesha7@gmail.com
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit bdb84a22b0)
The SPI-NAND layer default is on-die ECC because until now it was the
only one supported. New SPI-NAND chip flavors might use something else
as ECC engine provider but this will always be the default if the user
does not choose explicitly something else.
Change-Id: Ia437dda2d2a43007bf04e2e6a072610c283c97d6
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/20200930154109.3922-6-miquel.raynal@bootlin.com
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit c8efe01028)
Make use of the existing functions taken from the SPI-NAND core to
instantiate an on-die ECC engine specific to the SPI-NAND core. The
next step will be to tweak the core to use this object instead of
calling the helpers directly.
Change-Id: I91c0f9cd7da6f805fdd21b1a014c3446c6fa8813
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/20200930154109.3922-4-miquel.raynal@bootlin.com
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 945845b54c)
Prepare the creation of a SPI-NAND on-die ECC engine by gathering the
ECC-related code earlier enough in the core to avoid the need for
forward declarations.
The next step is to actually create that engine by implementing the
generic ECC interface.
Change-Id: I1730a95750b49f2f6653bbf8db81478e7819f4c6
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/20200930154109.3922-3-miquel.raynal@bootlin.com
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 55a1a71a7f)
The Macronix MX35LF1G24AD(/2G24AD/4G24AD) are 3V, 1G/2G/4Gbit serial
SLC NAND flash device (without on-die ECC).
Validated by read, erase, read back, write, read back on Xilinx Zynq
PicoZed FPGA board which included Macronix SPI Host(drivers/spi/spi-mxic.c)
& S/W BCH ecc(drivers/mtd/nand/ecc-sw-bch.c) with bug fixing patch
(mtd: nand: ecc-bch: Fix the size of calc_buf/code_buf of the BCH).
Change-Id: I88c68306bdc61a856cef9e5af1bc4c1e19fc2abd
Signed-off-by: YouChing Lin <ycllin@mxic.com.tw>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/1607570529-22341-3-git-send-email-ycllin@mxic.com.tw
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit ee4e0eafa4)
The Macronix MX35LF2GE4AD / MX35LF4GE4AD are 3V, 2G / 4Gbit serial
SLC NAND flash device (with on-die ECC).
Validated by read, erase, read back, write, read back and nandtest
on Xilinx Zynq PicoZed FPGA board which included Macronix SPI Host
(drivers/spi/spi-mxic.c).
Change-Id: I1603b4acd8c62720de245d70543b4743deaa7ad5
Signed-off-by: YouChing Lin <ycllin@mxic.com.tw>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/1604561020-13499-1-git-send-email-ycllin@mxic.com.tw
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 5ece78de88)
Using BBT in flash to avoid frequently flash operation for bbt info.
And it's secure to record the bad block info in bbt instead of
programing to the bad block with extremely unstable performance directly.
Change-Id: Icfe816c2c17ff3b747ce0a2512b1d9d6d0129fa0
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
In the unlikely event that both blocks 10 and 11 are marked as bad (on a
32 bit machine), then the process of marking block 10 as bad stomps on
cached entry for block 11. There are (of course) other examples.
Signed-off-by: Patrick Doyle <pdoyle@irobot.com>
Reviewed-by: Richard Weinberger <richard@nod.at>
Signed-off-by: Yoshio Furuyama <ytc-mb-yfuruyama7@kioxia.com>
[<miquel.raynal@bootlin.com>: Fixed the title]
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/774a92693f311e7de01e5935e720a179fb1b2468.1616635406.git.ytc-mb-yfuruyama7@kioxia.com
(cherry picked from commit fd0d8d85f7)
Change-Id: Ic3afc21e5f3e40950ed45036a41c57982983c70c
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Avoid the high 32btis input param of GENMASK bigger then BITS_PER_LONG.
For example offs 62, bits_per_block 3, and BITS_PER_LONG 64, then:
GENMASK(offs + bits_per_block - 1, offs) -> GENMASK(64, 62) -> 0.
But actually we want to mask GENMASK(63, 62) which is equals to
0xc000000000000000.
Change-Id: Ie3ee89a4b3e3deca45ccf429bfdfc5b88e3e6b9c
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
RK SDK solution develop a serials of support for better compatibility.
All of these is based on "spinand0" alias.
Change-Id: I6603221de66eb6a6cc8ebeafa42a0282d7ddd4e8
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
RK SDK solution develop a serials of support for better compatibility.
All of these is based on "sfc_nor" alias.
Change-Id: I4291a07420f4ad9f02a4d0ef3498061ae910cd7a
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
The new generic NAND ECC framework stores the configuration and
requirements in separate places since commit 93ef92f6f4 ("mtd: nand: Use
the new generic ECC object"). In 5.10.x The SPI NAND layer still uses only
the requirements to track the ECC properties. This mismatch leads to
values of zero being used for ECC strength and step_size in the SPI NAND
layer wherever nanddev_get_ecc_conf() is used and therefore breaks the SPI
NAND on-die ECC support in 5.10.x.
By using nanddev_get_ecc_requirements() instead of nanddev_get_ecc_conf()
for SPI NAND, we make sure that the correct parameters for the detected
chip are used. In later versions (5.11.x) this is fixed anyway with the
implementation of the SPI NAND on-die ECC engine.
Cc: stable@vger.kernel.org # 5.10.x
Reported-by: voice INTER connect GmbH <developer@voiceinterconnect.de>
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Acked-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
commit 2394e62873 upstream.
Erasing an AMD linear flash card (AM29F016D) crashes after the first
sector has been erased. Likewise, writing to it crashes after two bytes
have been written. The reason is a missing check for a null pointer -
the cmdset_priv field is not set for this type of card.
Fixes: 4844ef8030 ("mtd: cfi_cmdset_0002: Add support for polling status register")
Signed-off-by: Andreas Persson <andreasp56@outlook.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/DB6P189MB05830B3530B8087476C5CFE4C1159@DB6P189MB0583.EURP189.PROD.OUTLOOK.COM
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
[ Upstream commit b5437c7b68 ]
The controller being always asserting one CS or the other, there is no
need to actually select the right target before doing a page read/write.
However, the anfc_select_target() helper actually also changes the
timing configuration and clock in the case were two different NAND chips
with different timing requirements would be used. In this situation, we
must ensure proper configuration of the controller by calling it.
As a consequence of this change, the anfc_select_target() helper is
being moved earlier in the driver.
Fixes: 88ffef1b65 ("mtd: rawnand: arasan: Support the hardware BCH ECC engine")
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/20210526093242.183847-4-miquel.raynal@bootlin.com
Signed-off-by: Sasha Levin <sashal@kernel.org>
